mpc83xx.h 43 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __MPC83XX_H__
  6. #define __MPC83XX_H__
  7. #include <config.h>
  8. #include <asm/fsl_lbc.h>
  9. #if defined(CONFIG_E300)
  10. #include <asm/e300.h>
  11. #endif
  12. /*
  13. * System reset offset (PowerPC standard)
  14. */
  15. #define EXC_OFF_SYS_RESET 0x0100
  16. #define _START_OFFSET EXC_OFF_SYS_RESET
  17. /*
  18. * IMMRBAR - Internal Memory Register Base Address
  19. */
  20. /* Register offset to immr */
  21. #define IMMRBAR 0x0000
  22. #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
  23. #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
  24. /*
  25. * LAWBAR - Local Access Window Base Address Register
  26. */
  27. /* Register offset to immr */
  28. #define LBLAWBAR0 0x0020
  29. #define LBLAWAR0 0x0024
  30. #define LBLAWBAR1 0x0028
  31. #define LBLAWAR1 0x002C
  32. #define LBLAWBAR2 0x0030
  33. #define LBLAWAR2 0x0034
  34. #define LBLAWBAR3 0x0038
  35. #define LBLAWAR3 0x003C
  36. #define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */
  37. /*
  38. * SPRIDR - System Part and Revision ID Register
  39. */
  40. #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
  41. #define SPRIDR_REVID 0x0000FFFF /* Revision Id */
  42. #if defined(CONFIG_ARCH_MPC834X)
  43. #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
  44. #define REVID_MINOR(spridr) (spridr & 0x000000FF)
  45. #else
  46. #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
  47. #define REVID_MINOR(spridr) (spridr & 0x0000000F)
  48. #endif
  49. #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
  50. #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
  51. #define SPR_8308 0x8100
  52. #define SPR_8309 0x8110
  53. #define SPR_831X_FAMILY 0x80B
  54. #define SPR_8311 0x80B2
  55. #define SPR_8313 0x80B0
  56. #define SPR_8314 0x80B6
  57. #define SPR_8315 0x80B4
  58. #define SPR_832X_FAMILY 0x806
  59. #define SPR_8321 0x8066
  60. #define SPR_8323 0x8062
  61. #define SPR_834X_FAMILY 0x803
  62. #define SPR_8343 0x8036
  63. #define SPR_8347_TBGA_ 0x8032
  64. #define SPR_8347_PBGA_ 0x8034
  65. #define SPR_8349 0x8030
  66. #define SPR_836X_FAMILY 0x804
  67. #define SPR_8358_TBGA_ 0x804A
  68. #define SPR_8358_PBGA_ 0x804E
  69. #define SPR_8360 0x8048
  70. #define SPR_837X_FAMILY 0x80C
  71. #define SPR_8377 0x80C6
  72. #define SPR_8378 0x80C4
  73. #define SPR_8379 0x80C2
  74. /*
  75. * SPCR - System Priority Configuration Register
  76. */
  77. /* PCI Highest Priority Enable */
  78. #define SPCR_PCIHPE 0x10000000
  79. #define SPCR_PCIHPE_SHIFT (31-3)
  80. /* PCI bridge system bus request priority */
  81. #define SPCR_PCIPR 0x03000000
  82. #define SPCR_PCIPR_SHIFT (31-7)
  83. #define SPCR_OPT 0x00800000 /* Optimize */
  84. #define SPCR_OPT_SHIFT (31-8)
  85. /* E300 PowerPC core time base unit enable */
  86. #define SPCR_TBEN 0x00400000
  87. #define SPCR_TBEN_SHIFT (31-9)
  88. /* E300 PowerPC Core system bus request priority */
  89. #define SPCR_COREPR 0x00300000
  90. #define SPCR_COREPR_SHIFT (31-11)
  91. #if defined(CONFIG_ARCH_MPC834X)
  92. /* SPCR bits - MPC8349 specific */
  93. /* TSEC1 data priority */
  94. #define SPCR_TSEC1DP 0x00003000
  95. #define SPCR_TSEC1DP_SHIFT (31-19)
  96. /* TSEC1 buffer descriptor priority */
  97. #define SPCR_TSEC1BDP 0x00000C00
  98. #define SPCR_TSEC1BDP_SHIFT (31-21)
  99. /* TSEC1 emergency priority */
  100. #define SPCR_TSEC1EP 0x00000300
  101. #define SPCR_TSEC1EP_SHIFT (31-23)
  102. /* TSEC2 data priority */
  103. #define SPCR_TSEC2DP 0x00000030
  104. #define SPCR_TSEC2DP_SHIFT (31-27)
  105. /* TSEC2 buffer descriptor priority */
  106. #define SPCR_TSEC2BDP 0x0000000C
  107. #define SPCR_TSEC2BDP_SHIFT (31-29)
  108. /* TSEC2 emergency priority */
  109. #define SPCR_TSEC2EP 0x00000003
  110. #define SPCR_TSEC2EP_SHIFT (31-31)
  111. #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  112. defined(CONFIG_ARCH_MPC837X)
  113. /* SPCR bits - MPC8308, MPC831x and MPC837X specific */
  114. /* TSEC data priority */
  115. #define SPCR_TSECDP 0x00003000
  116. #define SPCR_TSECDP_SHIFT (31-19)
  117. /* TSEC buffer descriptor priority */
  118. #define SPCR_TSECBDP 0x00000C00
  119. #define SPCR_TSECBDP_SHIFT (31-21)
  120. /* TSEC emergency priority */
  121. #define SPCR_TSECEP 0x00000300
  122. #define SPCR_TSECEP_SHIFT (31-23)
  123. #endif
  124. /* SICRL/H - System I/O Configuration Register Low/High
  125. */
  126. #if defined(CONFIG_ARCH_MPC834X)
  127. /* SICRL bits - MPC8349 specific */
  128. #define SICRL_LDP_A 0x80000000
  129. #define SICRL_USB1 0x40000000
  130. #define SICRL_USB0 0x20000000
  131. #define SICRL_UART 0x0C000000
  132. #define SICRL_GPIO1_A 0x02000000
  133. #define SICRL_GPIO1_B 0x01000000
  134. #define SICRL_GPIO1_C 0x00800000
  135. #define SICRL_GPIO1_D 0x00400000
  136. #define SICRL_GPIO1_E 0x00200000
  137. #define SICRL_GPIO1_F 0x00180000
  138. #define SICRL_GPIO1_G 0x00040000
  139. #define SICRL_GPIO1_H 0x00020000
  140. #define SICRL_GPIO1_I 0x00010000
  141. #define SICRL_GPIO1_J 0x00008000
  142. #define SICRL_GPIO1_K 0x00004000
  143. #define SICRL_GPIO1_L 0x00003000
  144. /* SICRH bits - MPC8349 specific */
  145. #define SICRH_DDR 0x80000000
  146. #define SICRH_TSEC1_A 0x10000000
  147. #define SICRH_TSEC1_B 0x08000000
  148. #define SICRH_TSEC1_C 0x04000000
  149. #define SICRH_TSEC1_D 0x02000000
  150. #define SICRH_TSEC1_E 0x01000000
  151. #define SICRH_TSEC1_F 0x00800000
  152. #define SICRH_TSEC2_A 0x00400000
  153. #define SICRH_TSEC2_B 0x00200000
  154. #define SICRH_TSEC2_C 0x00100000
  155. #define SICRH_TSEC2_D 0x00080000
  156. #define SICRH_TSEC2_E 0x00040000
  157. #define SICRH_TSEC2_F 0x00020000
  158. #define SICRH_TSEC2_G 0x00010000
  159. #define SICRH_TSEC2_H 0x00008000
  160. #define SICRH_GPIO2_A 0x00004000
  161. #define SICRH_GPIO2_B 0x00002000
  162. #define SICRH_GPIO2_C 0x00001000
  163. #define SICRH_GPIO2_D 0x00000800
  164. #define SICRH_GPIO2_E 0x00000400
  165. #define SICRH_GPIO2_F 0x00000200
  166. #define SICRH_GPIO2_G 0x00000180
  167. #define SICRH_GPIO2_H 0x00000060
  168. #define SICRH_TSOBI1 0x00000002
  169. #define SICRH_TSOBI2 0x00000001
  170. #elif defined(CONFIG_ARCH_MPC8360)
  171. /* SICRL bits - MPC8360 specific */
  172. #define SICRL_LDP_A 0xC0000000
  173. #define SICRL_LCLK_1 0x10000000
  174. #define SICRL_LCLK_2 0x08000000
  175. #define SICRL_SRCID_A 0x03000000
  176. #define SICRL_IRQ_CKSTP_A 0x00C00000
  177. /* SICRH bits - MPC8360 specific */
  178. #define SICRH_DDR 0x80000000
  179. #define SICRH_SECONDARY_DDR 0x40000000
  180. #define SICRH_SDDROE 0x20000000
  181. #define SICRH_IRQ3 0x10000000
  182. #define SICRH_UC1EOBI 0x00000004
  183. #define SICRH_UC2E1OBI 0x00000002
  184. #define SICRH_UC2E2OBI 0x00000001
  185. #elif defined(CONFIG_ARCH_MPC832X)
  186. /* SICRL bits - MPC832x specific */
  187. #define SICRL_LDP_LCS_A 0x80000000
  188. #define SICRL_IRQ_CKS 0x20000000
  189. #define SICRL_PCI_MSRC 0x10000000
  190. #define SICRL_URT_CTPR 0x06000000
  191. #define SICRL_IRQ_CTPR 0x00C00000
  192. #elif defined(CONFIG_ARCH_MPC8313)
  193. /* SICRL bits - MPC8313 specific */
  194. #define SICRL_LBC 0x30000000
  195. #define SICRL_UART 0x0C000000
  196. #define SICRL_SPI_A 0x03000000
  197. #define SICRL_SPI_B 0x00C00000
  198. #define SICRL_SPI_C 0x00300000
  199. #define SICRL_SPI_D 0x000C0000
  200. #define SICRL_USBDR_11 0x00000C00
  201. #define SICRL_USBDR_10 0x00000800
  202. #define SICRL_USBDR_01 0x00000400
  203. #define SICRL_USBDR_00 0x00000000
  204. #define SICRL_ETSEC1_A 0x0000000C
  205. #define SICRL_ETSEC2_A 0x00000003
  206. /* SICRH bits - MPC8313 specific */
  207. #define SICRH_INTR_A 0x02000000
  208. #define SICRH_INTR_B 0x00C00000
  209. #define SICRH_IIC 0x00300000
  210. #define SICRH_ETSEC2_B 0x000C0000
  211. #define SICRH_ETSEC2_C 0x00030000
  212. #define SICRH_ETSEC2_D 0x0000C000
  213. #define SICRH_ETSEC2_E 0x00003000
  214. #define SICRH_ETSEC2_F 0x00000C00
  215. #define SICRH_ETSEC2_G 0x00000300
  216. #define SICRH_ETSEC1_B 0x00000080
  217. #define SICRH_ETSEC1_C 0x00000060
  218. #define SICRH_GTX1_DLY 0x00000008
  219. #define SICRH_GTX2_DLY 0x00000004
  220. #define SICRH_TSOBI1 0x00000002
  221. #define SICRH_TSOBI2 0x00000001
  222. #elif defined(CONFIG_ARCH_MPC837X)
  223. /* SICRL bits - MPC837X specific */
  224. #define SICRL_USB_A 0xC0000000
  225. #define SICRL_USB_B 0x30000000
  226. #define SICRL_USB_B_SD 0x20000000
  227. #define SICRL_UART 0x0C000000
  228. #define SICRL_GPIO_A 0x02000000
  229. #define SICRL_GPIO_B 0x01000000
  230. #define SICRL_GPIO_C 0x00800000
  231. #define SICRL_GPIO_D 0x00400000
  232. #define SICRL_GPIO_E 0x00200000
  233. #define SICRL_GPIO_F 0x00180000
  234. #define SICRL_GPIO_G 0x00040000
  235. #define SICRL_GPIO_H 0x00020000
  236. #define SICRL_GPIO_I 0x00010000
  237. #define SICRL_GPIO_J 0x00008000
  238. #define SICRL_GPIO_K 0x00004000
  239. #define SICRL_GPIO_L 0x00003000
  240. #define SICRL_DMA_A 0x00000800
  241. #define SICRL_DMA_B 0x00000400
  242. #define SICRL_DMA_C 0x00000200
  243. #define SICRL_DMA_D 0x00000100
  244. #define SICRL_DMA_E 0x00000080
  245. #define SICRL_DMA_F 0x00000040
  246. #define SICRL_DMA_G 0x00000020
  247. #define SICRL_DMA_H 0x00000010
  248. #define SICRL_DMA_I 0x00000008
  249. #define SICRL_DMA_J 0x00000004
  250. #define SICRL_LDP_A 0x00000002
  251. #define SICRL_LDP_B 0x00000001
  252. /* SICRH bits - MPC837X specific */
  253. #define SICRH_DDR 0x80000000
  254. #define SICRH_TSEC1_A 0x10000000
  255. #define SICRH_TSEC1_B 0x08000000
  256. #define SICRH_TSEC2_A 0x00400000
  257. #define SICRH_TSEC2_B 0x00200000
  258. #define SICRH_TSEC2_C 0x00100000
  259. #define SICRH_TSEC2_D 0x00080000
  260. #define SICRH_TSEC2_E 0x00040000
  261. #define SICRH_TMR 0x00010000
  262. #define SICRH_GPIO2_A 0x00008000
  263. #define SICRH_GPIO2_B 0x00004000
  264. #define SICRH_GPIO2_C 0x00002000
  265. #define SICRH_GPIO2_D 0x00001000
  266. #define SICRH_GPIO2_E 0x00000C00
  267. #define SICRH_GPIO2_E_SD 0x00000800
  268. #define SICRH_GPIO2_F 0x00000300
  269. #define SICRH_GPIO2_G 0x000000C0
  270. #define SICRH_GPIO2_H 0x00000030
  271. #define SICRH_SPI 0x00000003
  272. #define SICRH_SPI_SD 0x00000001
  273. #elif defined(CONFIG_ARCH_MPC8308)
  274. /* SICRL bits - MPC8308 specific */
  275. #define SICRL_SPI_PF0 (0 << 28)
  276. #define SICRL_SPI_PF1 (1 << 28)
  277. #define SICRL_SPI_PF3 (3 << 28)
  278. #define SICRL_UART_PF0 (0 << 26)
  279. #define SICRL_UART_PF1 (1 << 26)
  280. #define SICRL_UART_PF3 (3 << 26)
  281. #define SICRL_IRQ_PF0 (0 << 24)
  282. #define SICRL_IRQ_PF1 (1 << 24)
  283. #define SICRL_I2C2_PF0 (0 << 20)
  284. #define SICRL_I2C2_PF1 (1 << 20)
  285. #define SICRL_ETSEC1_TX_CLK (0 << 6)
  286. #define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
  287. /* SICRH bits - MPC8308 specific */
  288. #define SICRH_ESDHC_A_SD (0 << 30)
  289. #define SICRH_ESDHC_A_GTM (1 << 30)
  290. #define SICRH_ESDHC_A_GPIO (3 << 30)
  291. #define SICRH_ESDHC_B_SD (0 << 28)
  292. #define SICRH_ESDHC_B_GTM (1 << 28)
  293. #define SICRH_ESDHC_B_GPIO (3 << 28)
  294. #define SICRH_ESDHC_C_SD (0 << 26)
  295. #define SICRH_ESDHC_C_GTM (1 << 26)
  296. #define SICRH_ESDHC_C_GPIO (3 << 26)
  297. #define SICRH_GPIO_A_GPIO (0 << 24)
  298. #define SICRH_GPIO_A_TSEC2 (1 << 24)
  299. #define SICRH_GPIO_B_GPIO (0 << 22)
  300. #define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
  301. #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
  302. #define SICRH_IEEE1588_A_TMR (1 << 20)
  303. #define SICRH_IEEE1588_A_GPIO (3 << 20)
  304. #define SICRH_USB (1 << 18)
  305. #define SICRH_GTM_GTM (1 << 16)
  306. #define SICRH_GTM_GPIO (3 << 16)
  307. #define SICRH_IEEE1588_B_TMR (1 << 14)
  308. #define SICRH_IEEE1588_B_GPIO (3 << 14)
  309. #define SICRH_ETSEC2_CRS (1 << 12)
  310. #define SICRH_ETSEC2_GPIO (3 << 12)
  311. #define SICRH_GPIOSEL_0 (0 << 8)
  312. #define SICRH_GPIOSEL_1 (1 << 8)
  313. #define SICRH_TMROBI_V3P3 (0 << 4)
  314. #define SICRH_TMROBI_V2P5 (1 << 4)
  315. #define SICRH_TSOBI1_V3P3 (0 << 1)
  316. #define SICRH_TSOBI1_V2P5 (1 << 1)
  317. #define SICRH_TSOBI2_V3P3 (0 << 0)
  318. #define SICRH_TSOBI2_V2P5 (1 << 0)
  319. #endif
  320. /*
  321. * SWCRR - System Watchdog Control Register
  322. */
  323. /* Register offset to immr */
  324. #define SWCRR 0x0204
  325. /* Software Watchdog Time Count */
  326. #define SWCRR_SWTC 0xFFFF0000
  327. /* Watchdog Enable bit */
  328. #define SWCRR_SWEN 0x00000004
  329. /* Software Watchdog Reset/Interrupt Select bit */
  330. #define SWCRR_SWRI 0x00000002
  331. /* Software Watchdog Counter Prescale bit */
  332. #define SWCRR_SWPR 0x00000001
  333. #define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \
  334. SWCRR_SWRI | SWCRR_SWPR))
  335. /*
  336. * SWCNR - System Watchdog Counter Register
  337. */
  338. /* Register offset to immr */
  339. #define SWCNR 0x0208
  340. /* Software Watchdog Count mask */
  341. #define SWCNR_SWCN 0x0000FFFF
  342. #define SWCNR_RES ~(SWCNR_SWCN)
  343. /*
  344. * SWSRR - System Watchdog Service Register
  345. */
  346. /* Register offset to immr */
  347. #define SWSRR 0x020E
  348. /*
  349. * ACR - Arbiter Configuration Register
  350. */
  351. #define ACR_COREDIS 0x10000000 /* Core disable */
  352. #define ACR_COREDIS_SHIFT (31-7)
  353. #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
  354. #define ACR_PIPE_DEP_SHIFT (31-15)
  355. #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
  356. #define ACR_PCI_RPTCNT_SHIFT (31-19)
  357. #define ACR_RPTCNT 0x00000700 /* Repeat count */
  358. #define ACR_RPTCNT_SHIFT (31-23)
  359. #define ACR_APARK 0x00000030 /* Address parking */
  360. #define ACR_APARK_SHIFT (31-27)
  361. #define ACR_PARKM 0x0000000F /* Parking master */
  362. #define ACR_PARKM_SHIFT (31-31)
  363. /*
  364. * ATR - Arbiter Timers Register
  365. */
  366. #define ATR_DTO 0x00FF0000 /* Data time out */
  367. #define ATR_DTO_SHIFT 16
  368. #define ATR_ATO 0x000000FF /* Address time out */
  369. #define ATR_ATO_SHIFT 0
  370. /*
  371. * AER - Arbiter Event Register
  372. */
  373. #define AER_ETEA 0x00000020 /* Transfer error */
  374. /* Reserved transfer type */
  375. #define AER_RES 0x00000010
  376. /* External control word transfer type */
  377. #define AER_ECW 0x00000008
  378. /* Address Only transfer type */
  379. #define AER_AO 0x00000004
  380. #define AER_DTO 0x00000002 /* Data time out */
  381. #define AER_ATO 0x00000001 /* Address time out */
  382. /*
  383. * AEATR - Arbiter Event Address Register
  384. */
  385. #define AEATR_EVENT 0x07000000 /* Event type */
  386. #define AEATR_EVENT_SHIFT 24
  387. #define AEATR_MSTR_ID 0x001F0000 /* Master Id */
  388. #define AEATR_MSTR_ID_SHIFT 16
  389. #define AEATR_TBST 0x00000800 /* Transfer burst */
  390. #define AEATR_TBST_SHIFT 11
  391. #define AEATR_TSIZE 0x00000700 /* Transfer Size */
  392. #define AEATR_TSIZE_SHIFT 8
  393. #define AEATR_TTYPE 0x0000001F /* Transfer Type */
  394. #define AEATR_TTYPE_SHIFT 0
  395. /*
  396. * HRCWL - Hard Reset Configuration Word Low
  397. */
  398. #define HRCWL_LBIUCM 0x80000000
  399. #define HRCWL_LBIUCM_SHIFT 31
  400. #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
  401. #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
  402. #define HRCWL_DDRCM 0x40000000
  403. #define HRCWL_DDRCM_SHIFT 30
  404. #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
  405. #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
  406. #define HRCWL_SPMF 0x0f000000
  407. #define HRCWL_SPMF_SHIFT 24
  408. #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
  409. #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
  410. #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
  411. #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
  412. #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
  413. #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
  414. #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
  415. #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
  416. #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
  417. #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
  418. #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
  419. #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
  420. #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
  421. #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
  422. #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
  423. #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
  424. #define HRCWL_VCO_BYPASS 0x00000000
  425. #define HRCWL_VCO_1X2 0x00000000
  426. #define HRCWL_VCO_1X4 0x00200000
  427. #define HRCWL_VCO_1X8 0x00400000
  428. #define HRCWL_COREPLL 0x007F0000
  429. #define HRCWL_COREPLL_SHIFT 16
  430. #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
  431. #define HRCWL_CORE_TO_CSB_1X1 0x00020000
  432. #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
  433. #define HRCWL_CORE_TO_CSB_2X1 0x00040000
  434. #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
  435. #define HRCWL_CORE_TO_CSB_3X1 0x00060000
  436. #if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X)
  437. #define HRCWL_CEVCOD 0x000000C0
  438. #define HRCWL_CEVCOD_SHIFT 6
  439. #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
  440. #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
  441. #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
  442. #define HRCWL_CEPDF 0x00000020
  443. #define HRCWL_CEPDF_SHIFT 5
  444. #define HRCWL_CE_PLL_DIV_1X1 0x00000000
  445. #define HRCWL_CE_PLL_DIV_2X1 0x00000020
  446. #define HRCWL_CEPMF 0x0000001F
  447. #define HRCWL_CEPMF_SHIFT 0
  448. #define HRCWL_CE_TO_PLL_1X16_ 0x00000000
  449. #define HRCWL_CE_TO_PLL_1X2 0x00000002
  450. #define HRCWL_CE_TO_PLL_1X3 0x00000003
  451. #define HRCWL_CE_TO_PLL_1X4 0x00000004
  452. #define HRCWL_CE_TO_PLL_1X5 0x00000005
  453. #define HRCWL_CE_TO_PLL_1X6 0x00000006
  454. #define HRCWL_CE_TO_PLL_1X7 0x00000007
  455. #define HRCWL_CE_TO_PLL_1X8 0x00000008
  456. #define HRCWL_CE_TO_PLL_1X9 0x00000009
  457. #define HRCWL_CE_TO_PLL_1X10 0x0000000A
  458. #define HRCWL_CE_TO_PLL_1X11 0x0000000B
  459. #define HRCWL_CE_TO_PLL_1X12 0x0000000C
  460. #define HRCWL_CE_TO_PLL_1X13 0x0000000D
  461. #define HRCWL_CE_TO_PLL_1X14 0x0000000E
  462. #define HRCWL_CE_TO_PLL_1X15 0x0000000F
  463. #define HRCWL_CE_TO_PLL_1X16 0x00000010
  464. #define HRCWL_CE_TO_PLL_1X17 0x00000011
  465. #define HRCWL_CE_TO_PLL_1X18 0x00000012
  466. #define HRCWL_CE_TO_PLL_1X19 0x00000013
  467. #define HRCWL_CE_TO_PLL_1X20 0x00000014
  468. #define HRCWL_CE_TO_PLL_1X21 0x00000015
  469. #define HRCWL_CE_TO_PLL_1X22 0x00000016
  470. #define HRCWL_CE_TO_PLL_1X23 0x00000017
  471. #define HRCWL_CE_TO_PLL_1X24 0x00000018
  472. #define HRCWL_CE_TO_PLL_1X25 0x00000019
  473. #define HRCWL_CE_TO_PLL_1X26 0x0000001A
  474. #define HRCWL_CE_TO_PLL_1X27 0x0000001B
  475. #define HRCWL_CE_TO_PLL_1X28 0x0000001C
  476. #define HRCWL_CE_TO_PLL_1X29 0x0000001D
  477. #define HRCWL_CE_TO_PLL_1X30 0x0000001E
  478. #define HRCWL_CE_TO_PLL_1X31 0x0000001F
  479. #elif defined(CONFIG_ARCH_MPC8308)
  480. #define HRCWL_SVCOD 0x30000000
  481. #define HRCWL_SVCOD_SHIFT 28
  482. #define HRCWL_SVCOD_DIV_2 0x00000000
  483. #define HRCWL_SVCOD_DIV_4 0x10000000
  484. #define HRCWL_SVCOD_DIV_8 0x20000000
  485. #define HRCWL_SVCOD_DIV_1 0x30000000
  486. #elif defined(CONFIG_ARCH_MPC837X)
  487. #define HRCWL_SVCOD 0x30000000
  488. #define HRCWL_SVCOD_SHIFT 28
  489. #define HRCWL_SVCOD_DIV_4 0x00000000
  490. #define HRCWL_SVCOD_DIV_8 0x10000000
  491. #define HRCWL_SVCOD_DIV_2 0x20000000
  492. #define HRCWL_SVCOD_DIV_1 0x30000000
  493. #endif
  494. /*
  495. * HRCWH - Hardware Reset Configuration Word High
  496. */
  497. #define HRCWH_PCI_HOST 0x80000000
  498. #define HRCWH_PCI_HOST_SHIFT 31
  499. #define HRCWH_PCI_AGENT 0x00000000
  500. #if defined(CONFIG_ARCH_MPC834X)
  501. #define HRCWH_32_BIT_PCI 0x00000000
  502. #define HRCWH_64_BIT_PCI 0x40000000
  503. #endif
  504. #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
  505. #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
  506. #define HRCWH_PCI_ARBITER_DISABLE 0x00000000
  507. #define HRCWH_PCI_ARBITER_ENABLE 0x20000000
  508. #if defined(CONFIG_ARCH_MPC834X)
  509. #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
  510. #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
  511. #elif defined(CONFIG_ARCH_MPC8360)
  512. #define HRCWH_PCICKDRV_DISABLE 0x00000000
  513. #define HRCWH_PCICKDRV_ENABLE 0x10000000
  514. #endif
  515. #define HRCWH_CORE_DISABLE 0x08000000
  516. #define HRCWH_CORE_ENABLE 0x00000000
  517. #define HRCWH_FROM_0X00000100 0x00000000
  518. #define HRCWH_FROM_0XFFF00100 0x04000000
  519. #define HRCWH_BOOTSEQ_DISABLE 0x00000000
  520. #define HRCWH_BOOTSEQ_NORMAL 0x01000000
  521. #define HRCWH_BOOTSEQ_EXTENDED 0x02000000
  522. #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
  523. #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
  524. #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
  525. #define HRCWH_ROM_LOC_PCI1 0x00100000
  526. #if defined(CONFIG_ARCH_MPC834X)
  527. #define HRCWH_ROM_LOC_PCI2 0x00200000
  528. #endif
  529. #if defined(CONFIG_ARCH_MPC837X)
  530. #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
  531. #endif
  532. #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
  533. #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
  534. #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
  535. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  536. defined(CONFIG_ARCH_MPC837X)
  537. #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
  538. #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
  539. #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
  540. #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
  541. #define HRCWH_RL_EXT_LEGACY 0x00000000
  542. #define HRCWH_RL_EXT_NAND 0x00040000
  543. #define HRCWH_TSEC1M_MASK 0x0000E000
  544. #define HRCWH_TSEC1M_IN_MII 0x00000000
  545. #define HRCWH_TSEC1M_IN_RMII 0x00002000
  546. #define HRCWH_TSEC1M_IN_RGMII 0x00006000
  547. #define HRCWH_TSEC1M_IN_RTBI 0x0000A000
  548. #define HRCWH_TSEC1M_IN_SGMII 0x0000C000
  549. #define HRCWH_TSEC2M_MASK 0x00001C00
  550. #define HRCWH_TSEC2M_IN_MII 0x00000000
  551. #define HRCWH_TSEC2M_IN_RMII 0x00000400
  552. #define HRCWH_TSEC2M_IN_RGMII 0x00000C00
  553. #define HRCWH_TSEC2M_IN_RTBI 0x00001400
  554. #define HRCWH_TSEC2M_IN_SGMII 0x00001800
  555. #endif
  556. #if defined(CONFIG_ARCH_MPC834X)
  557. #define HRCWH_TSEC1M_IN_RGMII 0x00000000
  558. #define HRCWH_TSEC1M_IN_RTBI 0x00004000
  559. #define HRCWH_TSEC1M_IN_GMII 0x00008000
  560. #define HRCWH_TSEC1M_IN_TBI 0x0000C000
  561. #define HRCWH_TSEC2M_IN_RGMII 0x00000000
  562. #define HRCWH_TSEC2M_IN_RTBI 0x00001000
  563. #define HRCWH_TSEC2M_IN_GMII 0x00002000
  564. #define HRCWH_TSEC2M_IN_TBI 0x00003000
  565. #endif
  566. #if defined(CONFIG_ARCH_MPC8360)
  567. #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
  568. #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
  569. #endif
  570. #define HRCWH_BIG_ENDIAN 0x00000000
  571. #define HRCWH_LITTLE_ENDIAN 0x00000008
  572. #define HRCWH_LALE_NORMAL 0x00000000
  573. #define HRCWH_LALE_EARLY 0x00000004
  574. #define HRCWH_LDP_SET 0x00000000
  575. #define HRCWH_LDP_CLEAR 0x00000002
  576. /*
  577. * RSR - Reset Status Register
  578. */
  579. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  580. defined(CONFIG_ARCH_MPC837X)
  581. #define RSR_RSTSRC 0xF0000000 /* Reset source */
  582. #define RSR_RSTSRC_SHIFT 28
  583. #else
  584. #define RSR_RSTSRC 0xE0000000 /* Reset source */
  585. #define RSR_RSTSRC_SHIFT 29
  586. #endif
  587. #define RSR_BSF 0x00010000 /* Boot seq. fail */
  588. #define RSR_BSF_SHIFT 16
  589. /* software soft reset */
  590. #define RSR_SWSR 0x00002000
  591. #define RSR_SWSR_SHIFT 13
  592. /* software hard reset */
  593. #define RSR_SWHR 0x00001000
  594. #define RSR_SWHR_SHIFT 12
  595. #define RSR_JHRS 0x00000200 /* jtag hreset */
  596. #define RSR_JHRS_SHIFT 9
  597. /* jtag sreset status */
  598. #define RSR_JSRS 0x00000100
  599. #define RSR_JSRS_SHIFT 8
  600. /* checkstop reset status */
  601. #define RSR_CSHR 0x00000010
  602. #define RSR_CSHR_SHIFT 4
  603. /* software watchdog reset status */
  604. #define RSR_SWRS 0x00000008
  605. #define RSR_SWRS_SHIFT 3
  606. /* bus monitop reset status */
  607. #define RSR_BMRS 0x00000004
  608. #define RSR_BMRS_SHIFT 2
  609. #define RSR_SRS 0x00000002 /* soft reset status */
  610. #define RSR_SRS_SHIFT 1
  611. #define RSR_HRS 0x00000001 /* hard reset status */
  612. #define RSR_HRS_SHIFT 0
  613. #define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
  614. RSR_SWHR | RSR_JHRS | \
  615. RSR_JSRS | RSR_CSHR | \
  616. RSR_SWRS | RSR_BMRS | \
  617. RSR_SRS | RSR_HRS))
  618. /*
  619. * RMR - Reset Mode Register
  620. */
  621. /* checkstop reset enable */
  622. #define RMR_CSRE 0x00000001
  623. #define RMR_CSRE_SHIFT 0
  624. #define RMR_RES ~(RMR_CSRE)
  625. /*
  626. * RCR - Reset Control Register
  627. */
  628. /* software hard reset */
  629. #define RCR_SWHR 0x00000002
  630. /* software soft reset */
  631. #define RCR_SWSR 0x00000001
  632. #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
  633. /*
  634. * RCER - Reset Control Enable Register
  635. */
  636. /* software hard reset */
  637. #define RCER_CRE 0x00000001
  638. #define RCER_RES ~(RCER_CRE)
  639. /*
  640. * SPMR - System PLL Mode Register
  641. */
  642. #define SPMR_LBIUCM 0x80000000
  643. #define SPMR_LBIUCM_SHIFT 31
  644. #define SPMR_DDRCM 0x40000000
  645. #define SPMR_DDRCM_SHIFT 30
  646. #define SPMR_SPMF 0x0F000000
  647. #define SPMR_SPMF_SHIFT 24
  648. #define SPMR_CKID 0x00800000
  649. #define SPMR_CKID_SHIFT 23
  650. #define SPMR_COREPLL 0x007F0000
  651. #define SPMR_COREPLL_SHIFT 16
  652. #define SPMR_CEVCOD 0x000000C0
  653. #define SPMR_CEVCOD_SHIFT 6
  654. #define SPMR_CEPDF 0x00000020
  655. #define SPMR_CEPDF_SHIFT 5
  656. #define SPMR_CEPMF 0x0000001F
  657. #define SPMR_CEPMF_SHIFT 0
  658. /*
  659. * OCCR - Output Clock Control Register
  660. */
  661. #define OCCR_PCICOE0 0x80000000
  662. #define OCCR_PCICOE1 0x40000000
  663. #define OCCR_PCICOE2 0x20000000
  664. #define OCCR_PCICOE3 0x10000000
  665. #define OCCR_PCICOE4 0x08000000
  666. #define OCCR_PCICOE5 0x04000000
  667. #define OCCR_PCICOE6 0x02000000
  668. #define OCCR_PCICOE7 0x01000000
  669. #define OCCR_PCICD0 0x00800000
  670. #define OCCR_PCICD1 0x00400000
  671. #define OCCR_PCICD2 0x00200000
  672. #define OCCR_PCICD3 0x00100000
  673. #define OCCR_PCICD4 0x00080000
  674. #define OCCR_PCICD5 0x00040000
  675. #define OCCR_PCICD6 0x00020000
  676. #define OCCR_PCICD7 0x00010000
  677. #define OCCR_PCI1CR 0x00000002
  678. #define OCCR_PCI2CR 0x00000001
  679. #define OCCR_PCICR OCCR_PCI1CR
  680. /*
  681. * SCCR - System Clock Control Register
  682. */
  683. #define SCCR_ENCCM 0x03000000
  684. #define SCCR_ENCCM_SHIFT 24
  685. #define SCCR_ENCCM_0 0x00000000
  686. #define SCCR_ENCCM_1 0x01000000
  687. #define SCCR_ENCCM_2 0x02000000
  688. #define SCCR_ENCCM_3 0x03000000
  689. #define SCCR_PCICM 0x00010000
  690. #define SCCR_PCICM_SHIFT 16
  691. #if defined(CONFIG_ARCH_MPC834X)
  692. /* SCCR bits - MPC834X specific */
  693. #define SCCR_TSEC1CM 0xc0000000
  694. #define SCCR_TSEC1CM_SHIFT 30
  695. #define SCCR_TSEC1CM_0 0x00000000
  696. #define SCCR_TSEC1CM_1 0x40000000
  697. #define SCCR_TSEC1CM_2 0x80000000
  698. #define SCCR_TSEC1CM_3 0xC0000000
  699. #define SCCR_TSEC2CM 0x30000000
  700. #define SCCR_TSEC2CM_SHIFT 28
  701. #define SCCR_TSEC2CM_0 0x00000000
  702. #define SCCR_TSEC2CM_1 0x10000000
  703. #define SCCR_TSEC2CM_2 0x20000000
  704. #define SCCR_TSEC2CM_3 0x30000000
  705. /* The MPH must have the same clock ratio as DR, unless its clock disabled */
  706. #define SCCR_USBMPHCM 0x00c00000
  707. #define SCCR_USBMPHCM_SHIFT 22
  708. #define SCCR_USBDRCM 0x00300000
  709. #define SCCR_USBDRCM_SHIFT 20
  710. #define SCCR_USBCM 0x00f00000
  711. #define SCCR_USBCM_SHIFT 20
  712. #define SCCR_USBCM_0 0x00000000
  713. #define SCCR_USBCM_1 0x00500000
  714. #define SCCR_USBCM_2 0x00A00000
  715. #define SCCR_USBCM_3 0x00F00000
  716. #elif defined(CONFIG_ARCH_MPC8313)
  717. /* TSEC1 bits are for TSEC2 as well */
  718. #define SCCR_TSEC1CM 0xc0000000
  719. #define SCCR_TSEC1CM_SHIFT 30
  720. #define SCCR_TSEC1CM_0 0x00000000
  721. #define SCCR_TSEC1CM_1 0x40000000
  722. #define SCCR_TSEC1CM_2 0x80000000
  723. #define SCCR_TSEC1CM_3 0xC0000000
  724. #define SCCR_TSEC1ON 0x20000000
  725. #define SCCR_TSEC1ON_SHIFT 29
  726. #define SCCR_TSEC2ON 0x10000000
  727. #define SCCR_TSEC2ON_SHIFT 28
  728. #define SCCR_USBDRCM 0x00300000
  729. #define SCCR_USBDRCM_SHIFT 20
  730. #define SCCR_USBDRCM_0 0x00000000
  731. #define SCCR_USBDRCM_1 0x00100000
  732. #define SCCR_USBDRCM_2 0x00200000
  733. #define SCCR_USBDRCM_3 0x00300000
  734. #elif defined(CONFIG_ARCH_MPC8308)
  735. /* SCCR bits - MPC8315/MPC8308 specific */
  736. #define SCCR_TSEC1CM 0xc0000000
  737. #define SCCR_TSEC1CM_SHIFT 30
  738. #define SCCR_TSEC1CM_0 0x00000000
  739. #define SCCR_TSEC1CM_1 0x40000000
  740. #define SCCR_TSEC1CM_2 0x80000000
  741. #define SCCR_TSEC1CM_3 0xC0000000
  742. #define SCCR_TSEC2CM 0x30000000
  743. #define SCCR_TSEC2CM_SHIFT 28
  744. #define SCCR_TSEC2CM_0 0x00000000
  745. #define SCCR_TSEC2CM_1 0x10000000
  746. #define SCCR_TSEC2CM_2 0x20000000
  747. #define SCCR_TSEC2CM_3 0x30000000
  748. #define SCCR_SDHCCM 0x0c000000
  749. #define SCCR_SDHCCM_SHIFT 26
  750. #define SCCR_SDHCCM_0 0x00000000
  751. #define SCCR_SDHCCM_1 0x04000000
  752. #define SCCR_SDHCCM_2 0x08000000
  753. #define SCCR_SDHCCM_3 0x0c000000
  754. #define SCCR_USBDRCM 0x00c00000
  755. #define SCCR_USBDRCM_SHIFT 22
  756. #define SCCR_USBDRCM_0 0x00000000
  757. #define SCCR_USBDRCM_1 0x00400000
  758. #define SCCR_USBDRCM_2 0x00800000
  759. #define SCCR_USBDRCM_3 0x00c00000
  760. #define SCCR_SATA1CM 0x00003000
  761. #define SCCR_SATA1CM_SHIFT 12
  762. #define SCCR_SATACM 0x00003c00
  763. #define SCCR_SATACM_SHIFT 10
  764. #define SCCR_SATACM_0 0x00000000
  765. #define SCCR_SATACM_1 0x00001400
  766. #define SCCR_SATACM_2 0x00002800
  767. #define SCCR_SATACM_3 0x00003c00
  768. #define SCCR_TDMCM 0x00000030
  769. #define SCCR_TDMCM_SHIFT 4
  770. #define SCCR_TDMCM_0 0x00000000
  771. #define SCCR_TDMCM_1 0x00000010
  772. #define SCCR_TDMCM_2 0x00000020
  773. #define SCCR_TDMCM_3 0x00000030
  774. #elif defined(CONFIG_ARCH_MPC837X)
  775. /* SCCR bits - MPC837X specific */
  776. #define SCCR_TSEC1CM 0xc0000000
  777. #define SCCR_TSEC1CM_SHIFT 30
  778. #define SCCR_TSEC1CM_0 0x00000000
  779. #define SCCR_TSEC1CM_1 0x40000000
  780. #define SCCR_TSEC1CM_2 0x80000000
  781. #define SCCR_TSEC1CM_3 0xC0000000
  782. #define SCCR_TSEC2CM 0x30000000
  783. #define SCCR_TSEC2CM_SHIFT 28
  784. #define SCCR_TSEC2CM_0 0x00000000
  785. #define SCCR_TSEC2CM_1 0x10000000
  786. #define SCCR_TSEC2CM_2 0x20000000
  787. #define SCCR_TSEC2CM_3 0x30000000
  788. #define SCCR_SDHCCM 0x0c000000
  789. #define SCCR_SDHCCM_SHIFT 26
  790. #define SCCR_SDHCCM_0 0x00000000
  791. #define SCCR_SDHCCM_1 0x04000000
  792. #define SCCR_SDHCCM_2 0x08000000
  793. #define SCCR_SDHCCM_3 0x0c000000
  794. #define SCCR_USBDRCM 0x00c00000
  795. #define SCCR_USBDRCM_SHIFT 22
  796. #define SCCR_USBDRCM_0 0x00000000
  797. #define SCCR_USBDRCM_1 0x00400000
  798. #define SCCR_USBDRCM_2 0x00800000
  799. #define SCCR_USBDRCM_3 0x00c00000
  800. /* All of the four SATA controllers must have the same clock ratio */
  801. #define SCCR_SATA1CM 0x000000c0
  802. #define SCCR_SATA1CM_SHIFT 6
  803. #define SCCR_SATACM 0x000000ff
  804. #define SCCR_SATACM_SHIFT 0
  805. #define SCCR_SATACM_0 0x00000000
  806. #define SCCR_SATACM_1 0x00000055
  807. #define SCCR_SATACM_2 0x000000aa
  808. #define SCCR_SATACM_3 0x000000ff
  809. #endif
  810. #define SCCR_PCIEXP1CM 0x00300000
  811. #define SCCR_PCIEXP1CM_SHIFT 20
  812. #define SCCR_PCIEXP1CM_0 0x00000000
  813. #define SCCR_PCIEXP1CM_1 0x00100000
  814. #define SCCR_PCIEXP1CM_2 0x00200000
  815. #define SCCR_PCIEXP1CM_3 0x00300000
  816. #define SCCR_PCIEXP2CM 0x000c0000
  817. #define SCCR_PCIEXP2CM_SHIFT 18
  818. #define SCCR_PCIEXP2CM_0 0x00000000
  819. #define SCCR_PCIEXP2CM_1 0x00040000
  820. #define SCCR_PCIEXP2CM_2 0x00080000
  821. #define SCCR_PCIEXP2CM_3 0x000c0000
  822. /*
  823. * CSn_BDNS - Chip Select memory Bounds Register
  824. */
  825. #define CSBNDS_SA 0x00FF0000
  826. #define CSBNDS_SA_SHIFT 8
  827. #define CSBNDS_EA 0x000000FF
  828. #define CSBNDS_EA_SHIFT 24
  829. #ifndef CONFIG_MPC83XX_SDRAM
  830. /*
  831. * CSn_CONFIG - Chip Select Configuration Register
  832. */
  833. #define CSCONFIG_EN 0x80000000
  834. #define CSCONFIG_AP 0x00800000
  835. #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
  836. #define CSCONFIG_ODT_RD_NEVER 0x00000000
  837. #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
  838. #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
  839. #define CSCONFIG_ODT_RD_ALL 0x00400000
  840. #define CSCONFIG_ODT_WR_NEVER 0x00000000
  841. #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
  842. #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
  843. #define CSCONFIG_ODT_WR_ALL 0x00040000
  844. #elif defined(CONFIG_ARCH_MPC832X)
  845. #define CSCONFIG_ODT_RD_CFG 0x00400000
  846. #define CSCONFIG_ODT_WR_CFG 0x00040000
  847. #elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
  848. #define CSCONFIG_ODT_RD_NEVER 0x00000000
  849. #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
  850. #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
  851. #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
  852. #define CSCONFIG_ODT_RD_ALL 0x00400000
  853. #define CSCONFIG_ODT_WR_NEVER 0x00000000
  854. #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
  855. #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
  856. #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
  857. #define CSCONFIG_ODT_WR_ALL 0x00040000
  858. #endif
  859. #define CSCONFIG_BANK_BIT_3 0x00004000
  860. #define CSCONFIG_ROW_BIT 0x00000700
  861. #define CSCONFIG_ROW_BIT_12 0x00000000
  862. #define CSCONFIG_ROW_BIT_13 0x00000100
  863. #define CSCONFIG_ROW_BIT_14 0x00000200
  864. #define CSCONFIG_COL_BIT 0x00000007
  865. #define CSCONFIG_COL_BIT_8 0x00000000
  866. #define CSCONFIG_COL_BIT_9 0x00000001
  867. #define CSCONFIG_COL_BIT_10 0x00000002
  868. #define CSCONFIG_COL_BIT_11 0x00000003
  869. /*
  870. * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
  871. */
  872. #define TIMING_CFG0_RWT 0xC0000000
  873. #define TIMING_CFG0_RWT_SHIFT 30
  874. #define TIMING_CFG0_WRT 0x30000000
  875. #define TIMING_CFG0_WRT_SHIFT 28
  876. #define TIMING_CFG0_RRT 0x0C000000
  877. #define TIMING_CFG0_RRT_SHIFT 26
  878. #define TIMING_CFG0_WWT 0x03000000
  879. #define TIMING_CFG0_WWT_SHIFT 24
  880. #define TIMING_CFG0_ACT_PD_EXIT 0x00700000
  881. #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
  882. #define TIMING_CFG0_PRE_PD_EXIT 0x00070000
  883. #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
  884. #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
  885. #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
  886. #define TIMING_CFG0_MRS_CYC 0x0000000F
  887. #define TIMING_CFG0_MRS_CYC_SHIFT 0
  888. /*
  889. * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
  890. */
  891. #define TIMING_CFG1_PRETOACT 0x70000000
  892. #define TIMING_CFG1_PRETOACT_SHIFT 28
  893. #define TIMING_CFG1_ACTTOPRE 0x0F000000
  894. #define TIMING_CFG1_ACTTOPRE_SHIFT 24
  895. #define TIMING_CFG1_ACTTORW 0x00700000
  896. #define TIMING_CFG1_ACTTORW_SHIFT 20
  897. #define TIMING_CFG1_CASLAT 0x00070000
  898. #define TIMING_CFG1_CASLAT_SHIFT 16
  899. #define TIMING_CFG1_REFREC 0x0000F000
  900. #define TIMING_CFG1_REFREC_SHIFT 12
  901. #define TIMING_CFG1_WRREC 0x00000700
  902. #define TIMING_CFG1_WRREC_SHIFT 8
  903. #define TIMING_CFG1_ACTTOACT 0x00000070
  904. #define TIMING_CFG1_ACTTOACT_SHIFT 4
  905. #define TIMING_CFG1_WRTORD 0x00000007
  906. #define TIMING_CFG1_WRTORD_SHIFT 0
  907. #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
  908. #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
  909. #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
  910. #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
  911. #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
  912. #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
  913. #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
  914. /*
  915. * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  916. */
  917. #define TIMING_CFG2_CPO 0x0F800000
  918. #define TIMING_CFG2_CPO_SHIFT 23
  919. #define TIMING_CFG2_ACSM 0x00080000
  920. #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
  921. #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
  922. /* default (= CASLAT + 1) */
  923. #define TIMING_CFG2_CPO_DEF 0x00000000
  924. #define TIMING_CFG2_ADD_LAT 0x70000000
  925. #define TIMING_CFG2_ADD_LAT_SHIFT 28
  926. #define TIMING_CFG2_WR_LAT_DELAY 0x00380000
  927. #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
  928. #define TIMING_CFG2_RD_TO_PRE 0x0000E000
  929. #define TIMING_CFG2_RD_TO_PRE_SHIFT 13
  930. #define TIMING_CFG2_CKE_PLS 0x000001C0
  931. #define TIMING_CFG2_CKE_PLS_SHIFT 6
  932. #define TIMING_CFG2_FOUR_ACT 0x0000003F
  933. #define TIMING_CFG2_FOUR_ACT_SHIFT 0
  934. /*
  935. * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
  936. */
  937. #define TIMING_CFG3_EXT_REFREC 0x00070000
  938. #define TIMING_CFG3_EXT_REFREC_SHIFT 16
  939. /*
  940. * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  941. */
  942. #define SDRAM_CFG_MEM_EN 0x80000000
  943. #define SDRAM_CFG_SREN 0x40000000
  944. #define SDRAM_CFG_ECC_EN 0x20000000
  945. #define SDRAM_CFG_RD_EN 0x10000000
  946. #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
  947. #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
  948. #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
  949. #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
  950. #define SDRAM_CFG_DYN_PWR 0x00200000
  951. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  952. #define SDRAM_CFG_DBW_MASK 0x00180000
  953. #define SDRAM_CFG_DBW_16 0x00100000
  954. #define SDRAM_CFG_DBW_32 0x00080000
  955. #else
  956. #define SDRAM_CFG_32_BE 0x00080000
  957. #endif
  958. #if !defined(CONFIG_ARCH_MPC8308)
  959. #define SDRAM_CFG_8_BE 0x00040000
  960. #endif
  961. #define SDRAM_CFG_NCAP 0x00020000
  962. #define SDRAM_CFG_2T_EN 0x00008000
  963. #define SDRAM_CFG_HSE 0x00000008
  964. #define SDRAM_CFG_BI 0x00000001
  965. /*
  966. * DDR_SDRAM_MODE - DDR SDRAM Mode Register
  967. */
  968. #define SDRAM_MODE_ESD 0xFFFF0000
  969. #define SDRAM_MODE_ESD_SHIFT 16
  970. #define SDRAM_MODE_SD 0x0000FFFF
  971. #define SDRAM_MODE_SD_SHIFT 0
  972. /* select extended mode reg */
  973. #define DDR_MODE_EXT_MODEREG 0x4000
  974. /* operating mode, mask */
  975. #define DDR_MODE_EXT_OPMODE 0x3FF8
  976. #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
  977. /* QFC / compatibility, mask */
  978. #define DDR_MODE_QFC 0x0004
  979. /* compatible to older SDRAMs */
  980. #define DDR_MODE_QFC_COMP 0x0000
  981. /* weak drivers */
  982. #define DDR_MODE_WEAK 0x0002
  983. /* disable DLL */
  984. #define DDR_MODE_DLL_DIS 0x0001
  985. /* CAS latency, mask */
  986. #define DDR_MODE_CASLAT 0x0070
  987. #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
  988. #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
  989. #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
  990. #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
  991. /* sequential burst */
  992. #define DDR_MODE_BTYPE_SEQ 0x0000
  993. /* interleaved burst */
  994. #define DDR_MODE_BTYPE_ILVD 0x0008
  995. #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
  996. #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
  997. /* exact value for 7.8125us */
  998. #define DDR_REFINT_166MHZ_7US 1302
  999. /* use 256 cycles as a starting point */
  1000. #define DDR_BSTOPRE 256
  1001. /* select mode register */
  1002. #define DDR_MODE_MODEREG 0x0000
  1003. /*
  1004. * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
  1005. */
  1006. #define SDRAM_INTERVAL_REFINT 0x3FFF0000
  1007. #define SDRAM_INTERVAL_REFINT_SHIFT 16
  1008. #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
  1009. /*
  1010. * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
  1011. */
  1012. #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
  1013. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
  1014. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
  1015. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
  1016. #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
  1017. /*
  1018. * ECC_ERR_INJECT - Memory data path error injection mask ECC
  1019. */
  1020. /* ECC Mirror Byte */
  1021. #define ECC_ERR_INJECT_EMB (0x80000000 >> 22)
  1022. /* Error Injection Enable */
  1023. #define ECC_ERR_INJECT_EIEN (0x80000000 >> 23)
  1024. /* ECC Erroe Injection Enable */
  1025. #define ECC_ERR_INJECT_EEIM (0xff000000 >> 24)
  1026. #define ECC_ERR_INJECT_EEIM_SHIFT 0
  1027. /*
  1028. * CAPTURE_ECC - Memory data path read capture ECC
  1029. */
  1030. #define CAPTURE_ECC_ECE (0xff000000 >> 24)
  1031. #define CAPTURE_ECC_ECE_SHIFT 0
  1032. /*
  1033. * ERR_DETECT - Memory error detect
  1034. */
  1035. /* Multiple Memory Errors */
  1036. #define ECC_ERROR_DETECT_MME (0x80000000 >> 0)
  1037. /* Multiple-Bit Error */
  1038. #define ECC_ERROR_DETECT_MBE (0x80000000 >> 28)
  1039. /* Single-Bit ECC Error Pickup */
  1040. #define ECC_ERROR_DETECT_SBE (0x80000000 >> 29)
  1041. /* Memory Select Error */
  1042. #define ECC_ERROR_DETECT_MSE (0x80000000 >> 31)
  1043. /*
  1044. * ERR_DISABLE - Memory error disable
  1045. */
  1046. /* Multiple-Bit ECC Error Disable */
  1047. #define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28)
  1048. /* Sinle-Bit ECC Error disable */
  1049. #define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29)
  1050. /* Memory Select Error Disable */
  1051. #define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31)
  1052. #define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \
  1053. ECC_ERROR_DISABLE_SBED | \
  1054. ECC_ERROR_DISABLE_MBED))
  1055. /*
  1056. * ERR_INT_EN - Memory error interrupt enable
  1057. */
  1058. /* Multiple-Bit ECC Error Interrupt Enable */
  1059. #define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28)
  1060. /* Single-Bit ECC Error Interrupt Enable */
  1061. #define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29)
  1062. /* Memory Select Error Interrupt Enable */
  1063. #define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31)
  1064. #define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \
  1065. ECC_ERR_INT_EN_SBEE | \
  1066. ECC_ERR_INT_EN_MSEE))
  1067. /*
  1068. * CAPTURE_ATTRIBUTES - Memory error attributes capture
  1069. */
  1070. /* Data Beat Num */
  1071. #define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1)
  1072. #define ECC_CAPT_ATTR_BNUM_SHIFT 28
  1073. /* Transaction Size */
  1074. #define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6)
  1075. #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
  1076. #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
  1077. #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
  1078. #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
  1079. #define ECC_CAPT_ATTR_TSIZ_SHIFT 24
  1080. /* Transaction Source */
  1081. #define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11)
  1082. #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
  1083. #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
  1084. #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
  1085. #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
  1086. #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
  1087. #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
  1088. #define ECC_CAPT_ATTR_TSRC_I2C 0x9
  1089. #define ECC_CAPT_ATTR_TSRC_JTAG 0xA
  1090. #define ECC_CAPT_ATTR_TSRC_PCI1 0xD
  1091. #define ECC_CAPT_ATTR_TSRC_PCI2 0xE
  1092. #define ECC_CAPT_ATTR_TSRC_DMA 0xF
  1093. #define ECC_CAPT_ATTR_TSRC_SHIFT 16
  1094. /* Transaction Type */
  1095. #define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18)
  1096. #define ECC_CAPT_ATTR_TTYP_WRITE 0x1
  1097. #define ECC_CAPT_ATTR_TTYP_READ 0x2
  1098. #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
  1099. #define ECC_CAPT_ATTR_TTYP_SHIFT 12
  1100. #define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */
  1101. /*
  1102. * ERR_SBE - Single bit ECC memory error management
  1103. */
  1104. /* Single-Bit Error Threshold 0..255 */
  1105. #define ECC_ERROR_MAN_SBET (0xff000000 >> 8)
  1106. #define ECC_ERROR_MAN_SBET_SHIFT 16
  1107. /* Single Bit Error Counter 0..255 */
  1108. #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24)
  1109. #define ECC_ERROR_MAN_SBEC_SHIFT 0
  1110. #endif /* !CONFIG_MPC83XX_SDRAM */
  1111. /*
  1112. * PCI_CONFIG_ADDRESS - PCI Config Address Register
  1113. */
  1114. #define PCI_CONFIG_ADDRESS_EN 0x80000000
  1115. #define PCI_CONFIG_ADDRESS_BN_SHIFT 16
  1116. #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
  1117. #define PCI_CONFIG_ADDRESS_DN_SHIFT 11
  1118. #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
  1119. #define PCI_CONFIG_ADDRESS_FN_SHIFT 8
  1120. #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
  1121. #define PCI_CONFIG_ADDRESS_RN_SHIFT 0
  1122. #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
  1123. /*
  1124. * POTAR - PCI Outbound Translation Address Register
  1125. */
  1126. #define POTAR_TA_MASK 0x000fffff
  1127. /*
  1128. * POBAR - PCI Outbound Base Address Register
  1129. */
  1130. #define POBAR_BA_MASK 0x000fffff
  1131. /*
  1132. * POCMR - PCI Outbound Comparision Mask Register
  1133. */
  1134. #define POCMR_EN 0x80000000
  1135. /* 0-memory space 1-I/O space */
  1136. #define POCMR_IO 0x40000000
  1137. #define POCMR_SE 0x20000000 /* streaming enable */
  1138. #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
  1139. #define POCMR_CM_MASK 0x000fffff
  1140. #define POCMR_CM_4G 0x00000000
  1141. #define POCMR_CM_2G 0x00080000
  1142. #define POCMR_CM_1G 0x000C0000
  1143. #define POCMR_CM_512M 0x000E0000
  1144. #define POCMR_CM_256M 0x000F0000
  1145. #define POCMR_CM_128M 0x000F8000
  1146. #define POCMR_CM_64M 0x000FC000
  1147. #define POCMR_CM_32M 0x000FE000
  1148. #define POCMR_CM_16M 0x000FF000
  1149. #define POCMR_CM_8M 0x000FF800
  1150. #define POCMR_CM_4M 0x000FFC00
  1151. #define POCMR_CM_2M 0x000FFE00
  1152. #define POCMR_CM_1M 0x000FFF00
  1153. #define POCMR_CM_512K 0x000FFF80
  1154. #define POCMR_CM_256K 0x000FFFC0
  1155. #define POCMR_CM_128K 0x000FFFE0
  1156. #define POCMR_CM_64K 0x000FFFF0
  1157. #define POCMR_CM_32K 0x000FFFF8
  1158. #define POCMR_CM_16K 0x000FFFFC
  1159. #define POCMR_CM_8K 0x000FFFFE
  1160. #define POCMR_CM_4K 0x000FFFFF
  1161. /*
  1162. * PITAR - PCI Inbound Translation Address Register
  1163. */
  1164. #define PITAR_TA_MASK 0x000fffff
  1165. /*
  1166. * PIBAR - PCI Inbound Base/Extended Address Register
  1167. */
  1168. #define PIBAR_MASK 0xffffffff
  1169. #define PIEBAR_EBA_MASK 0x000fffff
  1170. /*
  1171. * PIWAR - PCI Inbound Windows Attributes Register
  1172. */
  1173. #define PIWAR_EN 0x80000000
  1174. #define PIWAR_PF 0x20000000
  1175. #define PIWAR_RTT_MASK 0x000f0000
  1176. #define PIWAR_RTT_NO_SNOOP 0x00040000
  1177. #define PIWAR_RTT_SNOOP 0x00050000
  1178. #define PIWAR_WTT_MASK 0x0000f000
  1179. #define PIWAR_WTT_NO_SNOOP 0x00004000
  1180. #define PIWAR_WTT_SNOOP 0x00005000
  1181. #define PIWAR_IWS_MASK 0x0000003F
  1182. #define PIWAR_IWS_4K 0x0000000B
  1183. #define PIWAR_IWS_8K 0x0000000C
  1184. #define PIWAR_IWS_16K 0x0000000D
  1185. #define PIWAR_IWS_32K 0x0000000E
  1186. #define PIWAR_IWS_64K 0x0000000F
  1187. #define PIWAR_IWS_128K 0x00000010
  1188. #define PIWAR_IWS_256K 0x00000011
  1189. #define PIWAR_IWS_512K 0x00000012
  1190. #define PIWAR_IWS_1M 0x00000013
  1191. #define PIWAR_IWS_2M 0x00000014
  1192. #define PIWAR_IWS_4M 0x00000015
  1193. #define PIWAR_IWS_8M 0x00000016
  1194. #define PIWAR_IWS_16M 0x00000017
  1195. #define PIWAR_IWS_32M 0x00000018
  1196. #define PIWAR_IWS_64M 0x00000019
  1197. #define PIWAR_IWS_128M 0x0000001A
  1198. #define PIWAR_IWS_256M 0x0000001B
  1199. #define PIWAR_IWS_512M 0x0000001C
  1200. #define PIWAR_IWS_1G 0x0000001D
  1201. #define PIWAR_IWS_2G 0x0000001E
  1202. /*
  1203. * PMCCR1 - PCI Configuration Register 1
  1204. */
  1205. #define PMCCR1_POWER_OFF 0x00000020
  1206. #ifndef CONFIG_RAM
  1207. /*
  1208. * DDRCDR - DDR Control Driver Register
  1209. */
  1210. #define DDRCDR_DHC_EN 0x80000000
  1211. #define DDRCDR_EN 0x40000000
  1212. #define DDRCDR_PZ 0x3C000000
  1213. #define DDRCDR_PZ_MAXZ 0x00000000
  1214. #define DDRCDR_PZ_HIZ 0x20000000
  1215. #define DDRCDR_PZ_NOMZ 0x30000000
  1216. #define DDRCDR_PZ_LOZ 0x38000000
  1217. #define DDRCDR_PZ_MINZ 0x3C000000
  1218. #define DDRCDR_NZ 0x3C000000
  1219. #define DDRCDR_NZ_MAXZ 0x00000000
  1220. #define DDRCDR_NZ_HIZ 0x02000000
  1221. #define DDRCDR_NZ_NOMZ 0x03000000
  1222. #define DDRCDR_NZ_LOZ 0x03800000
  1223. #define DDRCDR_NZ_MINZ 0x03C00000
  1224. #define DDRCDR_ODT 0x00080000
  1225. #define DDRCDR_DDR_CFG 0x00040000
  1226. #define DDRCDR_M_ODR 0x00000002
  1227. #define DDRCDR_Q_DRN 0x00000001
  1228. #endif /* !CONFIG_RAM */
  1229. /*
  1230. * PCIE Bridge Register
  1231. */
  1232. #define PEX_CSB_CTRL_OBPIOE 0x00000001
  1233. #define PEX_CSB_CTRL_IBPIOE 0x00000002
  1234. #define PEX_CSB_CTRL_WDMAE 0x00000004
  1235. #define PEX_CSB_CTRL_RDMAE 0x00000008
  1236. #define PEX_CSB_OBCTRL_PIOE 0x00000001
  1237. #define PEX_CSB_OBCTRL_MEMWE 0x00000002
  1238. #define PEX_CSB_OBCTRL_IOWE 0x00000004
  1239. #define PEX_CSB_OBCTRL_CFGWE 0x00000008
  1240. #define PEX_CSB_IBCTRL_PIOE 0x00000001
  1241. #define PEX_OWAR_EN 0x00000001
  1242. #define PEX_OWAR_TYPE_CFG 0x00000000
  1243. #define PEX_OWAR_TYPE_IO 0x00000002
  1244. #define PEX_OWAR_TYPE_MEM 0x00000004
  1245. #define PEX_OWAR_RLXO 0x00000008
  1246. #define PEX_OWAR_NANP 0x00000010
  1247. #define PEX_OWAR_SIZE 0xFFFFF000
  1248. #define PEX_IWAR_EN 0x00000001
  1249. #define PEX_IWAR_TYPE_INT 0x00000000
  1250. #define PEX_IWAR_TYPE_PF 0x00000004
  1251. #define PEX_IWAR_TYPE_NO_PF 0x00000006
  1252. #define PEX_IWAR_NSOV 0x00000008
  1253. #define PEX_IWAR_NSNP 0x00000010
  1254. #define PEX_IWAR_SIZE 0xFFFFF000
  1255. #define PEX_IWAR_SIZE_1M 0x000FF000
  1256. #define PEX_IWAR_SIZE_2M 0x001FF000
  1257. #define PEX_IWAR_SIZE_4M 0x003FF000
  1258. #define PEX_IWAR_SIZE_8M 0x007FF000
  1259. #define PEX_IWAR_SIZE_16M 0x00FFF000
  1260. #define PEX_IWAR_SIZE_32M 0x01FFF000
  1261. #define PEX_IWAR_SIZE_64M 0x03FFF000
  1262. #define PEX_IWAR_SIZE_128M 0x07FFF000
  1263. #define PEX_IWAR_SIZE_256M 0x0FFFF000
  1264. #define PEX_GCLK_RATIO 0x440
  1265. #ifndef __ASSEMBLY__
  1266. struct pci_region;
  1267. void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
  1268. void mpc83xx_pcislave_unlock(int bus);
  1269. void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
  1270. #endif
  1271. #endif /* __MPC83XX_H__ */