fsl_sec.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Common internal memory map for some Freescale SoCs
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. * Copyright 2018, 2021 NXP
  7. */
  8. #ifndef __FSL_SEC_H
  9. #define __FSL_SEC_H
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #ifdef CONFIG_SYS_FSL_SEC_LE
  13. #define sec_in32(a) in_le32((ulong *)(ulong)(a))
  14. #define sec_out32(a, v) out_le32((ulong *)(ulong)(a), v)
  15. #define sec_in16(a) in_le16(a)
  16. #define sec_clrbits32 clrbits_le32
  17. #define sec_setbits32 setbits_le32
  18. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  19. #define sec_in32(a) in_be32(a)
  20. #define sec_out32(a, v) out_be32(a, v)
  21. #define sec_in16(a) in_be16(a)
  22. #define sec_clrbits32 clrbits_be32
  23. #define sec_setbits32 setbits_be32
  24. #elif defined(CONFIG_SYS_FSL_HAS_SEC)
  25. #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
  26. #endif
  27. #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
  28. /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
  29. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  30. /* RNG4 TRNG test registers */
  31. struct rng4tst {
  32. #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
  33. #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
  34. both entropy shifter and
  35. statistical checker */
  36. #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
  37. entropy shifter and
  38. statistical checker */
  39. #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
  40. entropy shifter, raw data
  41. in statistical checker */
  42. #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
  43. u32 rtmctl; /* misc. control register */
  44. u32 rtscmisc; /* statistical check misc. register */
  45. u32 rtpkrrng; /* poker range register */
  46. #ifdef CONFIG_MX6SX
  47. #define RTSDCTL_ENT_DLY 12000
  48. #else
  49. #define RTSDCTL_ENT_DLY 3200
  50. #endif
  51. #define RTSDCTL_ENT_DLY_MAX 12800
  52. union {
  53. u32 rtpkrmax; /* PRGM=1: poker max. limit register */
  54. u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
  55. };
  56. #define RTSDCTL_ENT_DLY_SHIFT 16
  57. #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
  58. u32 rtsdctl; /* seed control register */
  59. union {
  60. u32 rtsblim; /* PRGM=1: sparse bit limit register */
  61. u32 rttotsam; /* PRGM=0: total samples register */
  62. };
  63. u32 rtfreqmin; /* frequency count min. limit register */
  64. #define RTFRQMAX_DISABLE (1 << 20)
  65. union {
  66. u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
  67. u32 rtfreqcnt; /* PRGM=0: freq. count register */
  68. };
  69. u32 rsvd1[40];
  70. #define RDSTA_IF(idx) (0x00000001 << (idx))
  71. #define RDSTA_PR(idx) (0x00000010 << (idx))
  72. #define RDSTA_MASK (RDSTA_PR(1) | RDSTA_PR(0) | RDSTA_IF(1) | RDSTA_IF(0))
  73. #define RDSTA_SKVN 0x40000000
  74. u32 rdsta; /*RNG DRNG Status Register*/
  75. u32 rsvd2[15];
  76. };
  77. /* Version registers (Era 10+) */
  78. struct version_regs {
  79. u32 crca; /* CRCA_VERSION */
  80. u32 afha; /* AFHA_VERSION */
  81. u32 kfha; /* KFHA_VERSION */
  82. u32 pkha; /* PKHA_VERSION */
  83. u32 aesa; /* AESA_VERSION */
  84. u32 mdha; /* MDHA_VERSION */
  85. u32 desa; /* DESA_VERSION */
  86. u32 snw8a; /* SNW8A_VERSION */
  87. u32 snw9a; /* SNW9A_VERSION */
  88. u32 zuce; /* ZUCE_VERSION */
  89. u32 zuca; /* ZUCA_VERSION */
  90. u32 ccha; /* CCHA_VERSION */
  91. u32 ptha; /* PTHA_VERSION */
  92. u32 rng; /* RNG_VERSION */
  93. u32 trng; /* TRNG_VERSION */
  94. u32 aaha; /* AAHA_VERSION */
  95. u32 rsvd[10];
  96. u32 sr; /* SR_VERSION */
  97. u32 dma; /* DMA_VERSION */
  98. u32 ai; /* AI_VERSION */
  99. u32 qi; /* QI_VERSION */
  100. u32 jr; /* JR_VERSION */
  101. u32 deco; /* DECO_VERSION */
  102. };
  103. #define CHA_VER_NUM_MASK 0x000000ff
  104. #define CHA_VER_MISC_SHIFT 8
  105. #define CHA_VER_MISC_MASK 0x0000ff00
  106. #define CHA_VER_REV_SHIFT 16
  107. #define CHA_VER_REV_MASK 0x00ff0000
  108. #define CHA_VER_VID_SHIFT 24
  109. #define CHA_VER_VID_MASK 0xff000000
  110. typedef struct ccsr_sec {
  111. u32 res0;
  112. u32 mcfgr; /* Master CFG Register */
  113. u8 res1[0x4];
  114. u32 scfgr;
  115. struct {
  116. u32 ms; /* Job Ring LIODN Register, MS */
  117. u32 ls; /* Job Ring LIODN Register, LS */
  118. } jrliodnr[4];
  119. u8 res2[0x2c];
  120. u32 jrstartr; /* Job Ring Start Register */
  121. struct {
  122. u32 ms; /* RTIC LIODN Register, MS */
  123. u32 ls; /* RTIC LIODN Register, LS */
  124. } rticliodnr[4];
  125. u8 res3[0x1c];
  126. u32 decorr; /* DECO Request Register */
  127. struct {
  128. u32 ms; /* DECO LIODN Register, MS */
  129. u32 ls; /* DECO LIODN Register, LS */
  130. } decoliodnr[16];
  131. u32 dar; /* DECO Avail Register */
  132. u32 drr; /* DECO Reset Register */
  133. u8 res5[0x4d8];
  134. struct rng4tst rng; /* RNG Registers */
  135. u8 res6[0x780];
  136. struct version_regs vreg; /* version registers since era 10 */
  137. u8 res7[0xa0];
  138. u32 crnr_ms; /* CHA Revision Number Register, MS */
  139. u32 crnr_ls; /* CHA Revision Number Register, LS */
  140. u32 ctpr_ms; /* Compile Time Parameters Register, MS */
  141. u32 ctpr_ls; /* Compile Time Parameters Register, LS */
  142. u8 res8[0x10];
  143. u32 far_ms; /* Fault Address Register, MS */
  144. u32 far_ls; /* Fault Address Register, LS */
  145. u32 falr; /* Fault Address LIODN Register */
  146. u32 fadr; /* Fault Address Detail Register */
  147. u8 res9[0x4];
  148. u32 csta; /* CAAM Status Register */
  149. u32 smpart; /* Secure Memory Partition Parameters */
  150. u32 smvid; /* Secure Memory Version ID */
  151. u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
  152. u32 ccbvid; /* CHA Cluster Block Version ID Register */
  153. u32 chavid_ms; /* CHA Version ID Register, MS */
  154. u32 chavid_ls; /* CHA Version ID Register, LS */
  155. u32 chanum_ms; /* CHA Number Register, MS */
  156. u32 chanum_ls; /* CHA Number Register, LS */
  157. u32 secvid_ms; /* SEC Version ID Register, MS */
  158. u32 secvid_ls; /* SEC Version ID Register, LS */
  159. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  160. u8 res10[0x6f020];
  161. #else
  162. u8 res10[0x6020];
  163. #endif
  164. u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
  165. u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
  166. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  167. u8 res11[0x8ffd8];
  168. #else
  169. u8 res11[0x8fd8];
  170. #endif
  171. } ccsr_sec_t;
  172. #define SEC_CTPR_MS_AXI_LIODN 0x08000000
  173. #define SEC_CTPR_MS_QI 0x02000000
  174. #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
  175. #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
  176. #define SEC_RVID_MA 0x0f000000
  177. #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
  178. #define SEC_CHANUM_MS_JRNUM_SHIFT 28
  179. #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
  180. #define SEC_CHANUM_MS_DECONUM_SHIFT 24
  181. #define SEC_SECVID_MS_IPID_MASK 0xffff0000
  182. #define SEC_SECVID_MS_IPID_SHIFT 16
  183. #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
  184. #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
  185. #define SEC_CCBVID_ERA_MASK 0xff000000
  186. #define SEC_CCBVID_ERA_SHIFT 24
  187. #define SEC_SCFGR_RDBENABLE 0x00000400
  188. #define SEC_SCFGR_VIRT_EN 0x00008000
  189. #define SEC_CHAVID_LS_RNG_SHIFT 16
  190. #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
  191. struct jr_regs {
  192. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  193. !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  194. defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
  195. u32 irba_l;
  196. u32 irba_h;
  197. #else
  198. u32 irba_h;
  199. u32 irba_l;
  200. #endif
  201. u32 rsvd1;
  202. u32 irs;
  203. u32 rsvd2;
  204. u32 irsa;
  205. u32 rsvd3;
  206. u32 irja;
  207. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  208. !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  209. defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
  210. u32 orba_l;
  211. u32 orba_h;
  212. #else
  213. u32 orba_h;
  214. u32 orba_l;
  215. #endif
  216. u32 rsvd4;
  217. u32 ors;
  218. u32 rsvd5;
  219. u32 orjr;
  220. u32 rsvd6;
  221. u32 orsf;
  222. u32 rsvd7;
  223. u32 jrsta;
  224. u32 rsvd8;
  225. u32 jrint;
  226. u32 jrcfg0;
  227. u32 jrcfg1;
  228. u32 rsvd9;
  229. u32 irri;
  230. u32 rsvd10;
  231. u32 orwi;
  232. u32 rsvd11;
  233. u32 jrcr;
  234. };
  235. /*
  236. * Scatter Gather Entry - Specifies the the Scatter Gather Format
  237. * related information
  238. */
  239. struct sg_entry {
  240. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  241. !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  242. defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
  243. uint32_t addr_lo; /* Memory Address - lo */
  244. uint32_t addr_hi; /* Memory Address of start of buffer - hi */
  245. #else
  246. uint32_t addr_hi; /* Memory Address of start of buffer - hi */
  247. uint32_t addr_lo; /* Memory Address - lo */
  248. #endif
  249. uint32_t len_flag; /* Length of the data in the frame */
  250. #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
  251. #define SG_ENTRY_EXTENSION_BIT 0x80000000
  252. #define SG_ENTRY_FINAL_BIT 0x40000000
  253. uint32_t bpid_offset;
  254. #define SG_ENTRY_BPID_MASK 0x00FF0000
  255. #define SG_ENTRY_BPID_SHIFT 16
  256. #define SG_ENTRY_OFFSET_MASK 0x00001FFF
  257. #define SG_ENTRY_OFFSET_SHIFT 0
  258. };
  259. #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  260. defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
  261. /* Job Ring Base Address */
  262. #define JR_BASE_ADDR(x) (CFG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
  263. /* Secure Memory Offset varies accross versions */
  264. #define SM_V1_OFFSET 0x0f4
  265. #define SM_V2_OFFSET 0xa00
  266. /*Secure Memory Versioning */
  267. #define SMVID_V2 0x20105
  268. #define SM_VERSION(x) ({typeof(x) _x = x; \
  269. _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); })
  270. #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
  271. /* CAAM Job Ring 0 Registers */
  272. /* Secure Memory Partition Owner register */
  273. #define SMCSJR_PO (3 << 6)
  274. /* JR Allocation Error */
  275. #define SMCSJR_AERR (3 << 12)
  276. /* Secure memory partition 0 page 0 owner register */
  277. #define CAAM_SMPO_0 (CFG_SYS_FSL_SEC_ADDR + 0x1FBC)
  278. /* Secure memory command register */
  279. #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
  280. /* Secure memory command status register */
  281. #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
  282. /* Secure memory access permissions register */
  283. #define CAAM_SMAPJR(v, jr, y) \
  284. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
  285. /* Secure memory access group 2 register */
  286. #define CAAM_SMAG2JR(v, jr, y) \
  287. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
  288. /* Secure memory access group 1 register */
  289. #define CAAM_SMAG1JR(v, jr, y) \
  290. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
  291. /* Commands and macros for secure memory */
  292. #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
  293. #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
  294. #define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
  295. #define SM_GROUP2(v) ({typeof(v) _v = v; \
  296. _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); })
  297. #define SM_GROUP1(v) ({typeof(v) _v = v; \
  298. _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); })
  299. #define CMD_PAGE_ALLOC 0x1
  300. #define CMD_PAGE_DEALLOC 0x2
  301. #define CMD_PART_DEALLOC 0x3
  302. #define CMD_INQUIRY 0x5
  303. #define CMD_COMPLETE (3 << 14)
  304. #define PAGE_AVAILABLE 0
  305. #define PAGE_OWNED (3 << 6)
  306. #define PAGE(x) (x << 16)
  307. #define PARTITION(x) (x << 8)
  308. #define PARTITION_OWNER(x) (0x3 << (x*2))
  309. /* Address of secure 4kbyte pages */
  310. #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
  311. #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
  312. #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
  313. #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
  314. #ifdef CONFIG_IMX8M
  315. #define JR_MID (1) /* Matches ATF configuration */
  316. #define KS_G1 (0x10000 << JR_MID) /* CAAM only */
  317. #define PERM (0xB080) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
  318. #else
  319. #define JR_MID (2) /* Matches ROM configuration */
  320. #define KS_G1 BIT(JR_MID) /* CAAM only */
  321. #define PERM (0xB008) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */
  322. #endif /* CONFIG_IMX8M */
  323. /* HAB WRAPPED KEY header */
  324. #define WRP_HDR_SIZE 0x08
  325. #define HDR_TAG 0x81
  326. #define HDR_PAR 0x41
  327. /* HAB WRAPPED KEY Data */
  328. #define HAB_MOD 0x66
  329. #define HAB_ALG 0x55
  330. #define HAB_FLG 0x00
  331. /* Partition and Page IDs */
  332. #define PARTITION_1 1
  333. #define PAGE_1 1
  334. #define ERROR_IN_PAGE_ALLOC 1
  335. #define ECONSTRJDESC -1
  336. #endif
  337. #define FSL_CAAM_MP_PUBK_BYTES 64
  338. #define FSL_CAAM_MP_PRVK_BYTES 32
  339. #define FSL_CAAM_MP_MES_DGST_BYTES 32
  340. #define FSL_CAAM_ORSR_JRa_OFFSET 0x102c
  341. #define FSL_CAAM_MAX_JR_SIZE 4
  342. /* blob_dek:
  343. * Encapsulates the src in a secure blob and stores it dst
  344. * @src: reference to the plaintext
  345. * @dst: reference to the output adrress
  346. * @len: size in bytes of src
  347. * @return: 0 on success, error otherwise
  348. */
  349. int blob_dek(const u8 *src, u8 *dst, u8 len);
  350. int gen_mppubk(u8 *dst);
  351. int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d);
  352. #if defined(CONFIG_ARCH_C29X)
  353. int sec_init_idx(uint8_t);
  354. #endif
  355. int sec_init(void);
  356. u8 caam_get_era(void);
  357. #endif
  358. #endif /* __FSL_SEC_H */