Kconfig 13 KB

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  1. config ARCH_MAP_SYSMEM
  2. depends on SANDBOX
  3. def_bool y
  4. config CREATE_ARCH_SYMLINK
  5. bool
  6. config HAVE_ARCH_IOREMAP
  7. bool
  8. config SYS_CACHE_SHIFT_4
  9. bool
  10. config SYS_CACHE_SHIFT_5
  11. bool
  12. config SYS_CACHE_SHIFT_6
  13. bool
  14. config SYS_CACHE_SHIFT_7
  15. bool
  16. config SYS_CACHELINE_SIZE
  17. int
  18. default 128 if SYS_CACHE_SHIFT_7
  19. default 64 if SYS_CACHE_SHIFT_6
  20. default 32 if SYS_CACHE_SHIFT_5
  21. default 16 if SYS_CACHE_SHIFT_4
  22. # Fall-back for MIPS
  23. default 32 if MIPS
  24. config LINKER_LIST_ALIGN
  25. int
  26. default 32 if SANDBOX
  27. default 8 if ARM64 || X86
  28. default 4
  29. help
  30. Force the each linker list to be aligned to this boundary. This
  31. is required if ll_entry_get() is used, since otherwise the linker
  32. may add padding into the table, thus breaking it.
  33. See linker_lists.rst for full details.
  34. choice
  35. prompt "Architecture select"
  36. default SANDBOX
  37. config ARC
  38. bool "ARC architecture"
  39. select ARC_TIMER
  40. select CLK
  41. select DM
  42. select HAVE_PRIVATE_LIBGCC
  43. select SUPPORT_OF_CONTROL
  44. select SYS_CACHE_SHIFT_7
  45. select TIMER
  46. select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
  47. select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
  48. config ARM
  49. bool "ARM architecture"
  50. select ARCH_SUPPORTS_LTO
  51. select CREATE_ARCH_SYMLINK
  52. select HAVE_PRIVATE_LIBGCC if !ARM64
  53. select SUPPORT_ACPI
  54. select SUPPORT_OF_CONTROL
  55. config M68K
  56. bool "M68000 architecture"
  57. select HAVE_PRIVATE_LIBGCC
  58. select USE_PRIVATE_LIBGCC
  59. select NEEDS_MANUAL_RELOC
  60. select SYS_BOOT_GET_CMDLINE
  61. select SYS_BOOT_GET_KBD
  62. select SYS_CACHE_SHIFT_4
  63. select SUPPORT_OF_CONTROL
  64. config MICROBLAZE
  65. bool "MicroBlaze architecture"
  66. select SUPPORT_OF_CONTROL
  67. imply CMD_TIMER
  68. imply SPL_REGMAP if SPL
  69. imply SPL_TIMER if SPL
  70. imply TIMER
  71. imply XILINX_TIMER
  72. config MIPS
  73. bool "MIPS architecture"
  74. select HAVE_ARCH_IOREMAP
  75. select HAVE_PRIVATE_LIBGCC
  76. select SUPPORT_OF_CONTROL
  77. select SPL_SEPARATE_BSS if SPL
  78. config NIOS2
  79. bool "Nios II architecture"
  80. select CPU
  81. select DM
  82. select DM_EVENT
  83. select OF_CONTROL
  84. select SUPPORT_OF_CONTROL
  85. imply CMD_DM
  86. config PPC
  87. bool "PowerPC architecture"
  88. select HAVE_PRIVATE_LIBGCC
  89. select SUPPORT_OF_CONTROL
  90. select SYS_BOOT_GET_CMDLINE
  91. select SYS_BOOT_GET_KBD
  92. config RISCV
  93. bool "RISC-V architecture"
  94. select CREATE_ARCH_SYMLINK
  95. select SUPPORT_OF_CONTROL
  96. select OF_CONTROL
  97. select DM
  98. select DM_EVENT
  99. imply SPL_SEPARATE_BSS if SPL
  100. imply DM_SERIAL
  101. imply DM_MMC
  102. imply DM_SPI
  103. imply DM_SPI_FLASH
  104. imply BLK
  105. imply CLK
  106. imply MTD
  107. imply TIMER
  108. imply CMD_DM
  109. imply SPL_DM
  110. imply SPL_OF_CONTROL
  111. imply SPL_LIBCOMMON_SUPPORT
  112. imply SPL_LIBGENERIC_SUPPORT
  113. imply SPL_SERIAL
  114. imply SPL_TIMER
  115. config SANDBOX
  116. bool "Sandbox"
  117. select ARCH_SUPPORTS_LTO
  118. select BOARD_LATE_INIT
  119. select BZIP2
  120. select CMD_POWEROFF
  121. select DM
  122. select DM_EVENT
  123. select DM_FUZZING_ENGINE
  124. select DM_GPIO
  125. select DM_I2C
  126. select DM_KEYBOARD
  127. select DM_MMC
  128. select DM_SERIAL
  129. select DM_SPI
  130. select DM_SPI_FLASH
  131. select GZIP_COMPRESSED
  132. select IO_TRACE
  133. select LZO
  134. select OF_BOARD_SETUP
  135. select PCI_ENDPOINT
  136. select SPI
  137. select SUPPORT_OF_CONTROL
  138. select SYSRESET_CMD_POWEROFF
  139. select SYS_CACHE_SHIFT_4
  140. select IRQ
  141. select SUPPORT_EXTENSION_SCAN
  142. select SUPPORT_ACPI
  143. imply BITREVERSE
  144. select BLOBLIST
  145. imply LTO
  146. imply CMD_DM
  147. imply CMD_EXCEPTION
  148. imply CMD_GETTIME
  149. imply CMD_HASH
  150. imply CMD_IO
  151. imply CMD_IOTRACE
  152. imply CMD_LZMADEC
  153. imply CMD_SF
  154. imply CMD_SF_TEST
  155. imply CRC32_VERIFY
  156. imply FAT_WRITE
  157. imply FIRMWARE
  158. imply FUZZING_ENGINE_SANDBOX
  159. imply HASH_VERIFY
  160. imply LZMA
  161. imply TEE
  162. imply AVB_VERIFY
  163. imply LIBAVB
  164. imply CMD_AVB
  165. imply PARTITION_TYPE_GUID
  166. imply SCP03
  167. imply CMD_SCP03
  168. imply UDP_FUNCTION_FASTBOOT
  169. imply VIRTIO_MMIO
  170. imply VIRTIO_PCI
  171. imply VIRTIO_SANDBOX
  172. imply VIRTIO_BLK
  173. imply VIRTIO_NET
  174. imply DM_SOUND
  175. imply PCI_SANDBOX_EP
  176. imply PCH
  177. imply PHYLIB
  178. imply DM_MDIO
  179. imply DM_MDIO_MUX
  180. imply ACPI
  181. imply ACPI_PMC
  182. imply ACPI_PMC_SANDBOX
  183. imply CMD_PMC
  184. imply CMD_CLONE
  185. imply SILENT_CONSOLE
  186. imply BOOTARGS_SUBST
  187. imply PHY_FIXED
  188. imply DM_DSA
  189. imply CMD_EXTENSION
  190. imply KEYBOARD
  191. imply PHYSMEM
  192. imply GENERATE_ACPI_TABLE
  193. imply BINMAN
  194. config SH
  195. bool "SuperH architecture"
  196. select HAVE_PRIVATE_LIBGCC
  197. select SUPPORT_OF_CONTROL
  198. config X86
  199. bool "x86 architecture"
  200. select SUPPORT_SPL
  201. select SUPPORT_TPL
  202. select CREATE_ARCH_SYMLINK
  203. select DM
  204. select HAVE_ARCH_IOMAP
  205. select HAVE_PRIVATE_LIBGCC
  206. select OF_CONTROL
  207. select PCI
  208. select SUPPORT_ACPI
  209. select SUPPORT_OF_CONTROL
  210. select SYS_CACHE_SHIFT_6
  211. select TIMER
  212. select USE_PRIVATE_LIBGCC
  213. select X86_TSC_TIMER
  214. select IRQ
  215. imply HAS_ROM if X86_RESET_VECTOR
  216. imply BLK
  217. imply CMD_DM
  218. imply CMD_FPGA_LOADMK
  219. imply CMD_GETTIME
  220. imply CMD_IO
  221. imply CMD_IRQ
  222. imply CMD_PCI
  223. imply CMD_SF
  224. imply CMD_SF_TEST
  225. imply CMD_ZBOOT
  226. imply DM_GPIO
  227. imply DM_KEYBOARD
  228. imply DM_MMC
  229. imply DM_RTC
  230. imply DM_SCSI
  231. imply DM_SERIAL
  232. imply DM_SPI
  233. imply DM_SPI_FLASH
  234. imply DM_USB
  235. imply VIDEO
  236. imply SYSRESET
  237. imply SPL_SYSRESET
  238. imply SYSRESET_X86
  239. imply USB_ETHER_ASIX
  240. imply USB_ETHER_SMSC95XX
  241. imply USB_HOST_ETHER
  242. imply PCH
  243. imply PHYSMEM
  244. imply RTC_MC146818
  245. imply ACPI
  246. imply ACPIGEN if !QEMU && !EFI_APP
  247. imply SYSINFO if GENERATE_SMBIOS_TABLE
  248. imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
  249. imply TIMESTAMP
  250. # Thing to enable for when SPL/TPL are enabled: SPL
  251. imply SPL_DM
  252. imply SPL_OF_LIBFDT
  253. imply SPL_DRIVERS_MISC
  254. imply SPL_GPIO
  255. imply SPL_PINCTRL
  256. imply SPL_LIBCOMMON_SUPPORT
  257. imply SPL_LIBGENERIC_SUPPORT
  258. imply SPL_SERIAL
  259. imply SPL_SPI_FLASH_SUPPORT
  260. imply SPL_SPI
  261. imply SPL_OF_CONTROL
  262. imply SPL_TIMER
  263. imply SPL_REGMAP
  264. imply SPL_SYSCON
  265. # TPL
  266. imply TPL_DM
  267. imply TPL_DRIVERS_MISC
  268. imply TPL_GPIO
  269. imply TPL_PINCTRL
  270. imply TPL_LIBCOMMON_SUPPORT
  271. imply TPL_LIBGENERIC_SUPPORT
  272. imply TPL_SERIAL
  273. imply TPL_OF_CONTROL
  274. imply TPL_TIMER
  275. imply TPL_REGMAP
  276. imply TPL_SYSCON
  277. config XTENSA
  278. bool "Xtensa architecture"
  279. select CREATE_ARCH_SYMLINK
  280. select SUPPORT_OF_CONTROL
  281. endchoice
  282. config SYS_ARCH
  283. string
  284. help
  285. This option should contain the architecture name to build the
  286. appropriate arch/<CONFIG_SYS_ARCH> directory.
  287. All the architectures should specify this option correctly.
  288. config SYS_CPU
  289. string
  290. help
  291. This option should contain the CPU name to build the correct
  292. arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
  293. This is optional. For those targets without the CPU directory,
  294. leave this option empty.
  295. config SYS_SOC
  296. string
  297. help
  298. This option should contain the SoC name to build the directory
  299. arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
  300. This is optional. For those targets without the SoC directory,
  301. leave this option empty.
  302. config SYS_VENDOR
  303. string
  304. help
  305. This option should contain the vendor name of the target board.
  306. If it is set and
  307. board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
  308. directory is compiled.
  309. If CONFIG_SYS_BOARD is also set, the sources under
  310. board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
  311. This is optional. For those targets without the vendor directory,
  312. leave this option empty.
  313. config SYS_BOARD
  314. string
  315. help
  316. This option should contain the name of the target board.
  317. If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
  318. or board/<CONFIG_SYS_BOARD> directory is compiled depending on
  319. whether CONFIG_SYS_VENDOR is set or not.
  320. This is optional. For those targets without the board directory,
  321. leave this option empty.
  322. config SYS_CONFIG_NAME
  323. string
  324. help
  325. This option should contain the base name of board header file.
  326. The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
  327. should be included from include/config.h.
  328. config SYS_DISABLE_DCACHE_OPS
  329. bool
  330. help
  331. This option disables dcache flush and dcache invalidation
  332. operations. For example, on coherent systems where cache
  333. operatios are not required, enable this option to avoid them.
  334. Note that, its up to the individual architectures to implement
  335. this functionality.
  336. config SYS_IMMR
  337. hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
  338. depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
  339. default 0xFF000000 if MPC8xx
  340. default 0xF0000000 if ARCH_MPC8313
  341. default 0xE0000000 if MPC83xx && !ARCH_MPC8313
  342. default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
  343. default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
  344. ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
  345. ARCH_P2020
  346. default SYS_CCSRBAR_DEFAULT
  347. help
  348. Address for the Internal Memory-Mapped Registers (IMMR) window used
  349. to configure the features of many Freescale / NXP SoCs.
  350. config MONITOR_IS_IN_RAM
  351. bool "U-Boot is loaded in to RAM by a pre-loader"
  352. depends on M68K || NIOS2
  353. menu "Skipping low level initialization functions"
  354. depends on ARM || MIPS || RISCV
  355. config SKIP_LOWLEVEL_INIT
  356. bool "Skip calls to certain low level initialization functions"
  357. help
  358. If enabled, then certain low level initializations (like setting up
  359. the memory controller) are omitted and/or U-Boot does not relocate
  360. itself into RAM.
  361. Normally this variable MUST NOT be defined. The only exception is
  362. when U-Boot is loaded (to RAM) by some other boot loader or by a
  363. debugger which performs these initializations itself.
  364. config SPL_SKIP_LOWLEVEL_INIT
  365. bool "Skip calls to certain low level initialization functions in SPL"
  366. depends on SPL
  367. help
  368. If enabled, then certain low level initializations (like setting up
  369. the memory controller) are omitted and/or U-Boot does not relocate
  370. itself into RAM.
  371. Normally this variable MUST NOT be defined. The only exception is
  372. when U-Boot is loaded (to RAM) by some other boot loader or by a
  373. debugger which performs these initializations itself.
  374. config TPL_SKIP_LOWLEVEL_INIT
  375. bool "Skip calls to certain low level initialization functions in TPL"
  376. depends on SPL && ARM
  377. help
  378. If enabled, then certain low level initializations (like setting up
  379. the memory controller) are omitted and/or U-Boot does not relocate
  380. itself into RAM.
  381. Normally this variable MUST NOT be defined. The only exception is
  382. when U-Boot is loaded (to RAM) by some other boot loader or by a
  383. debugger which performs these initializations itself.
  384. config SKIP_LOWLEVEL_INIT_ONLY
  385. bool "Skip call to lowlevel_init during early boot ONLY"
  386. depends on ARM
  387. help
  388. This allows just the call to lowlevel_init() to be skipped. The
  389. normal CP15 init (such as enabling the instruction cache) is still
  390. performed.
  391. config SPL_SKIP_LOWLEVEL_INIT_ONLY
  392. bool "Skip call to lowlevel_init during early SPL boot ONLY"
  393. depends on SPL && ARM
  394. help
  395. This allows just the call to lowlevel_init() to be skipped. The
  396. normal CP15 init (such as enabling the instruction cache) is still
  397. performed.
  398. config TPL_SKIP_LOWLEVEL_INIT_ONLY
  399. bool "Skip call to lowlevel_init during early TPL boot ONLY"
  400. depends on TPL && ARM
  401. help
  402. This allows just the call to lowlevel_init() to be skipped. The
  403. normal CP15 init (such as enabling the instruction cache) is still
  404. performed.
  405. endmenu
  406. config SYS_HAS_NONCACHED_MEMORY
  407. bool "Enable reserving a non-cached memory area for drivers"
  408. depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
  409. help
  410. This is useful for drivers that would otherwise require a lot of
  411. explicit cache maintenance. For some drivers it's also impossible to
  412. properly maintain the cache. For example if the regions that need to
  413. be flushed are not a multiple of the cache-line size, *and* padding
  414. cannot be allocated between the regions to align them (i.e. if the
  415. HW requires a contiguous array of regions, and the size of each
  416. region is not cache-aligned), then a flush of one region may result
  417. in overwriting data that hardware has written to another region in
  418. the same cache-line. This can happen for example in network drivers
  419. where descriptors for buffers are typically smaller than the CPU
  420. cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
  421. config SYS_NONCACHED_MEMORY
  422. hex "Size in bytes of the non-cached memory area"
  423. depends on SYS_HAS_NONCACHED_MEMORY
  424. default 0x100000
  425. help
  426. Size of non-cached memory area. This area of memory will be typically
  427. located right below the malloc() area and mapped uncached in the MMU.
  428. source "arch/arc/Kconfig"
  429. source "arch/arm/Kconfig"
  430. source "arch/m68k/Kconfig"
  431. source "arch/microblaze/Kconfig"
  432. source "arch/mips/Kconfig"
  433. source "arch/nios2/Kconfig"
  434. source "arch/powerpc/Kconfig"
  435. source "arch/sandbox/Kconfig"
  436. source "arch/sh/Kconfig"
  437. source "arch/x86/Kconfig"
  438. source "arch/xtensa/Kconfig"
  439. source "arch/riscv/Kconfig"
  440. if ARM || M68K || PPC
  441. source "arch/Kconfig.nxp"
  442. endif
  443. source "board/keymile/Kconfig"
  444. if MIPS || MICROBLAZE
  445. choice
  446. prompt "Endianness selection"
  447. help
  448. Some MIPS boards can be configured for either little or big endian
  449. byte order. These modes require different U-Boot images. In general there
  450. is one preferred byteorder for a particular system but some systems are
  451. just as commonly used in the one or the other endianness.
  452. config SYS_BIG_ENDIAN
  453. bool "Big endian"
  454. depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
  455. config SYS_LITTLE_ENDIAN
  456. bool "Little endian"
  457. depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
  458. endchoice
  459. endif