ls2080ardb.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017, 2019-2021 NXP
  4. * Copyright 2015 Freescale Semiconductor
  5. */
  6. #ifndef __LS2_RDB_H
  7. #define __LS2_RDB_H
  8. #include "ls2080a_common.h"
  9. #ifdef CONFIG_FSL_QSPI
  10. #ifdef CONFIG_TARGET_LS2081ARDB
  11. #define CONFIG_QIXIS_I2C_ACCESS
  12. #endif
  13. #endif
  14. #define I2C_MUX_CH_VOL_MONITOR 0xa
  15. #define I2C_VOL_MONITOR_ADDR 0x38
  16. /* step the IR regulator in 5mV increments */
  17. #define IR_VDD_STEP_DOWN 5
  18. #define IR_VDD_STEP_UP 5
  19. /* The lowest and highest voltage allowed for LS2080ARDB */
  20. #define VDD_MV_MIN 819
  21. #define VDD_MV_MAX 1212
  22. #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
  23. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  24. #define SPD_EEPROM_ADDRESS1 0x51
  25. #define SPD_EEPROM_ADDRESS2 0x52
  26. #define SPD_EEPROM_ADDRESS3 0x53
  27. #define SPD_EEPROM_ADDRESS4 0x54
  28. #define SPD_EEPROM_ADDRESS5 0x55
  29. #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
  30. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  31. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  32. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  33. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  34. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  35. #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
  36. #endif
  37. /* SATA */
  38. #define CONFIG_SCSI_AHCI_PLAT
  39. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  40. #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
  41. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  42. #define CONFIG_SYS_SCSI_MAX_LUN 1
  43. #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  44. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  45. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  46. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  47. #define CONFIG_SYS_NOR0_CSPR \
  48. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  49. CSPR_PORT_SIZE_16 | \
  50. CSPR_MSEL_NOR | \
  51. CSPR_V)
  52. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  53. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  54. CSPR_PORT_SIZE_16 | \
  55. CSPR_MSEL_NOR | \
  56. CSPR_V)
  57. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  58. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  59. FTIM0_NOR_TEADC(0x5) | \
  60. FTIM0_NOR_TEAHC(0x5))
  61. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  62. FTIM1_NOR_TRAD_NOR(0x1a) |\
  63. FTIM1_NOR_TSEQRAD_NOR(0x13))
  64. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  65. FTIM2_NOR_TCH(0x4) | \
  66. FTIM2_NOR_TWPH(0x0E) | \
  67. FTIM2_NOR_TWP(0x1c))
  68. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  69. #define CONFIG_SYS_IFC_CCR 0x01000000
  70. #ifdef CONFIG_MTD_NOR_FLASH
  71. #define CONFIG_SYS_FLASH_QUIET_TEST
  72. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  73. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  74. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  75. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  76. #define CONFIG_SYS_FLASH_EMPTY_INFO
  77. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
  78. CONFIG_SYS_FLASH_BASE + 0x40000000}
  79. #endif
  80. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  81. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  82. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  83. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  84. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  85. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  86. | CSPR_V)
  87. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  88. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  89. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  90. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  91. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  92. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  93. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  94. | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
  95. /* ONFI NAND Flash mode0 Timing Params */
  96. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
  97. FTIM0_NAND_TWP(0x30) | \
  98. FTIM0_NAND_TWCHT(0x0e) | \
  99. FTIM0_NAND_TWH(0x14))
  100. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
  101. FTIM1_NAND_TWBE(0xab) | \
  102. FTIM1_NAND_TRR(0x1c) | \
  103. FTIM1_NAND_TRP(0x30))
  104. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
  105. FTIM2_NAND_TREH(0x14) | \
  106. FTIM2_NAND_TWHRE(0x3c))
  107. #define CONFIG_SYS_NAND_FTIM3 0x0
  108. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  109. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  110. #define CONFIG_MTD_NAND_VERIFY_WRITE
  111. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  112. #define QIXIS_LBMAP_SWITCH 0x06
  113. #define QIXIS_LBMAP_MASK 0x0f
  114. #define QIXIS_LBMAP_SHIFT 0
  115. #define QIXIS_LBMAP_DFLTBANK 0x00
  116. #define QIXIS_LBMAP_ALTBANK 0x04
  117. #define QIXIS_LBMAP_NAND 0x09
  118. #define QIXIS_RST_CTL_RESET 0x31
  119. #define QIXIS_RST_CTL_RESET_EN 0x30
  120. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  121. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  122. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  123. #define QIXIS_RCW_SRC_NAND 0x119
  124. #define QIXIS_RST_FORCE_MEM 0x01
  125. #define CONFIG_SYS_CSPR3_EXT (0x0)
  126. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  127. | CSPR_PORT_SIZE_8 \
  128. | CSPR_MSEL_GPCM \
  129. | CSPR_V)
  130. #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  131. | CSPR_PORT_SIZE_8 \
  132. | CSPR_MSEL_GPCM \
  133. | CSPR_V)
  134. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  135. #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
  136. /* QIXIS Timing parameters for IFC CS3 */
  137. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  138. FTIM0_GPCM_TEADC(0x0e) | \
  139. FTIM0_GPCM_TEAHC(0x0e))
  140. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  141. FTIM1_GPCM_TRAD(0x3f))
  142. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  143. FTIM2_GPCM_TCH(0xf) | \
  144. FTIM2_GPCM_TWP(0x3E))
  145. #define CONFIG_SYS_CS3_FTIM3 0x0
  146. #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
  147. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  148. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
  149. #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
  150. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  151. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  152. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  153. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  154. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  155. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  156. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  157. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  158. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  159. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  160. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  161. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  162. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  163. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  164. #define CONFIG_SPL_PAD_TO 0x80000
  165. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
  166. #else
  167. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  168. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  169. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  170. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  171. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  172. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  173. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  174. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  175. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  176. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  177. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  178. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  179. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  180. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  181. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  182. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  183. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  184. #endif
  185. /* Debug Server firmware */
  186. #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  187. #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
  188. #endif
  189. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  190. #ifdef CONFIG_TARGET_LS2081ARDB
  191. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  192. #define QIXIS_QMAP_MASK 0x07
  193. #define QIXIS_QMAP_SHIFT 5
  194. #define QIXIS_LBMAP_DFLTBANK 0x00
  195. #define QIXIS_LBMAP_QSPI 0x00
  196. #define QIXIS_RCW_SRC_QSPI 0x62
  197. #define QIXIS_LBMAP_ALTBANK 0x20
  198. #define QIXIS_RST_CTL_RESET 0x31
  199. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  200. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  201. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  202. #define QIXIS_LBMAP_MASK 0x0f
  203. #define QIXIS_RST_CTL_RESET_EN 0x30
  204. #endif
  205. /*
  206. * I2C
  207. */
  208. #ifdef CONFIG_TARGET_LS2081ARDB
  209. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  210. #endif
  211. #define I2C_MUX_PCA_ADDR 0x75
  212. #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
  213. /* I2C bus multiplexer */
  214. #define I2C_MUX_CH_DEFAULT 0x8
  215. /* SPI */
  216. /*
  217. * RTC configuration
  218. */
  219. #define RTC
  220. #ifdef CONFIG_TARGET_LS2081ARDB
  221. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  222. #else
  223. #define CONFIG_RTC_DS3231 1
  224. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  225. #endif
  226. /* EEPROM */
  227. #define CONFIG_SYS_I2C_EEPROM_NXID
  228. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  229. #define CONFIG_FSL_MEMAC
  230. #ifdef CONFIG_PCI
  231. #define CONFIG_PCI_SCAN_SHOW
  232. #endif
  233. #define BOOT_TARGET_DEVICES(func) \
  234. func(USB, usb, 0) \
  235. func(MMC, mmc, 0) \
  236. func(SCSI, scsi, 0) \
  237. func(DHCP, dhcp, na)
  238. #include <config_distro_bootcmd.h>
  239. #ifdef CONFIG_TFABOOT
  240. #define QSPI_MC_INIT_CMD \
  241. "sf probe 0:0; " \
  242. "sf read 0x80640000 0x640000 0x80000; " \
  243. "env exists secureboot && " \
  244. "esbc_validate 0x80640000 && " \
  245. "esbc_validate 0x80680000; " \
  246. "sf read 0x80a00000 0xa00000 0x200000; " \
  247. "sf read 0x80e00000 0xe00000 0x100000; " \
  248. "fsl_mc start mc 0x80a00000 0x80e00000 \0"
  249. #define SD_MC_INIT_CMD \
  250. "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
  251. "mmc read 0x80e00000 0x7000 0x800;" \
  252. "env exists secureboot && " \
  253. "mmc read 0x80640000 0x3200 0x20 && " \
  254. "mmc read 0x80680000 0x3400 0x20 && " \
  255. "esbc_validate 0x80640000 && " \
  256. "esbc_validate 0x80680000 ;" \
  257. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  258. #define IFC_MC_INIT_CMD \
  259. "env exists secureboot && " \
  260. "esbc_validate 0x580640000 && " \
  261. "esbc_validate 0x580680000; " \
  262. "fsl_mc start mc 0x580a00000 0x580e00000 \0"
  263. #else
  264. #ifdef CONFIG_QSPI_BOOT
  265. #define MC_INIT_CMD \
  266. "mcinitcmd=sf probe 0:0; " \
  267. "sf read 0x80640000 0x640000 0x80000; " \
  268. "env exists secureboot && " \
  269. "esbc_validate 0x80640000 && " \
  270. "esbc_validate 0x80680000; " \
  271. "sf read 0x80a00000 0xa00000 0x200000; " \
  272. "sf read 0x80e00000 0xe00000 0x100000; " \
  273. "fsl_mc start mc 0x80a00000 0x80e00000 \0"
  274. #elif defined(CONFIG_SD_BOOT)
  275. #define MC_INIT_CMD \
  276. "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
  277. "mmc read 0x80e00000 0x7000 0x800;" \
  278. "env exists secureboot && " \
  279. "mmc read 0x80640000 0x3200 0x20 && " \
  280. "mmc read 0x80680000 0x3400 0x20 && " \
  281. "esbc_validate 0x80640000 && " \
  282. "esbc_validate 0x80680000 ;" \
  283. "fsl_mc start mc 0x80a00000 0x80e00000\0" \
  284. "mcmemsize=0x70000000\0"
  285. #else
  286. #define MC_INIT_CMD \
  287. "mcinitcmd=env exists secureboot && " \
  288. "esbc_validate 0x580640000 && " \
  289. "esbc_validate 0x580680000; " \
  290. "fsl_mc start mc 0x580a00000 0x580e00000 \0"
  291. #endif
  292. #endif
  293. /* Initial environment variables */
  294. #undef CONFIG_EXTRA_ENV_SETTINGS
  295. #ifdef CONFIG_TFABOOT
  296. #define CONFIG_EXTRA_ENV_SETTINGS \
  297. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  298. "ramdisk_addr=0x800000\0" \
  299. "ramdisk_size=0x2000000\0" \
  300. "fdt_high=0xa0000000\0" \
  301. "initrd_high=0xffffffffffffffff\0" \
  302. "fdt_addr=0x64f00000\0" \
  303. "kernel_addr=0x581000000\0" \
  304. "kernel_start=0x1000000\0" \
  305. "kernelheader_start=0x800000\0" \
  306. "scriptaddr=0x80000000\0" \
  307. "scripthdraddr=0x80080000\0" \
  308. "fdtheader_addr_r=0x80100000\0" \
  309. "kernelheader_addr_r=0x80200000\0" \
  310. "kernelheader_addr=0x580600000\0" \
  311. "kernel_addr_r=0x81000000\0" \
  312. "kernelheader_size=0x40000\0" \
  313. "fdt_addr_r=0x90000000\0" \
  314. "load_addr=0xa0000000\0" \
  315. "kernel_size=0x2800000\0" \
  316. "kernel_addr_sd=0x8000\0" \
  317. "kernel_size_sd=0x14000\0" \
  318. "console=ttyAMA0,38400n8\0" \
  319. "mcmemsize=0x70000000\0" \
  320. "sd_bootcmd=echo Trying load from SD ..;" \
  321. "mmcinfo; mmc read $load_addr " \
  322. "$kernel_addr_sd $kernel_size_sd && " \
  323. "bootm $load_addr#$board\0" \
  324. QSPI_MC_INIT_CMD \
  325. BOOTENV \
  326. "boot_scripts=ls2088ardb_boot.scr\0" \
  327. "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
  328. "scan_dev_for_boot_part=" \
  329. "part list ${devtype} ${devnum} devplist; " \
  330. "env exists devplist || setenv devplist 1; " \
  331. "for distro_bootpart in ${devplist}; do " \
  332. "if fstype ${devtype} " \
  333. "${devnum}:${distro_bootpart} " \
  334. "bootfstype; then " \
  335. "run scan_dev_for_boot; " \
  336. "fi; " \
  337. "done\0" \
  338. "boot_a_script=" \
  339. "load ${devtype} ${devnum}:${distro_bootpart} " \
  340. "${scriptaddr} ${prefix}${script}; " \
  341. "env exists secureboot && load ${devtype} " \
  342. "${devnum}:${distro_bootpart} " \
  343. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  344. "&& esbc_validate ${scripthdraddr};" \
  345. "source ${scriptaddr}\0" \
  346. "qspi_bootcmd=echo Trying load from qspi..;" \
  347. "sf probe && sf read $load_addr " \
  348. "$kernel_start $kernel_size ; env exists secureboot &&" \
  349. "sf read $kernelheader_addr_r $kernelheader_start " \
  350. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  351. " bootm $load_addr#$board\0" \
  352. "nor_bootcmd=echo Trying load from nor..;" \
  353. "cp.b $kernel_addr $load_addr " \
  354. "$kernel_size ; env exists secureboot && " \
  355. "cp.b $kernelheader_addr $kernelheader_addr_r " \
  356. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  357. "bootm $load_addr#$board\0"
  358. #else
  359. #define CONFIG_EXTRA_ENV_SETTINGS \
  360. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  361. "ramdisk_addr=0x800000\0" \
  362. "ramdisk_size=0x2000000\0" \
  363. "fdt_high=0xa0000000\0" \
  364. "initrd_high=0xffffffffffffffff\0" \
  365. "fdt_addr=0x64f00000\0" \
  366. "kernel_addr=0x581000000\0" \
  367. "kernel_start=0x1000000\0" \
  368. "kernelheader_start=0x600000\0" \
  369. "scriptaddr=0x80000000\0" \
  370. "scripthdraddr=0x80080000\0" \
  371. "fdtheader_addr_r=0x80100000\0" \
  372. "kernelheader_addr_r=0x80200000\0" \
  373. "kernelheader_addr=0x580600000\0" \
  374. "kernel_addr_r=0x81000000\0" \
  375. "kernelheader_size=0x40000\0" \
  376. "fdt_addr_r=0x90000000\0" \
  377. "load_addr=0xa0000000\0" \
  378. "kernel_size=0x2800000\0" \
  379. "kernel_addr_sd=0x8000\0" \
  380. "kernel_size_sd=0x14000\0" \
  381. "console=ttyAMA0,38400n8\0" \
  382. "mcmemsize=0x70000000\0" \
  383. "sd_bootcmd=echo Trying load from SD ..;" \
  384. "mmcinfo; mmc read $load_addr " \
  385. "$kernel_addr_sd $kernel_size_sd && " \
  386. "bootm $load_addr#$board\0" \
  387. MC_INIT_CMD \
  388. BOOTENV \
  389. "boot_scripts=ls2088ardb_boot.scr\0" \
  390. "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
  391. "scan_dev_for_boot_part=" \
  392. "part list ${devtype} ${devnum} devplist; " \
  393. "env exists devplist || setenv devplist 1; " \
  394. "for distro_bootpart in ${devplist}; do " \
  395. "if fstype ${devtype} " \
  396. "${devnum}:${distro_bootpart} " \
  397. "bootfstype; then " \
  398. "run scan_dev_for_boot; " \
  399. "fi; " \
  400. "done\0" \
  401. "boot_a_script=" \
  402. "load ${devtype} ${devnum}:${distro_bootpart} " \
  403. "${scriptaddr} ${prefix}${script}; " \
  404. "env exists secureboot && load ${devtype} " \
  405. "${devnum}:${distro_bootpart} " \
  406. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  407. "env exists secureboot " \
  408. "&& esbc_validate ${scripthdraddr};" \
  409. "source ${scriptaddr}\0" \
  410. "qspi_bootcmd=echo Trying load from qspi..;" \
  411. "sf probe && sf read $load_addr " \
  412. "$kernel_start $kernel_size ; env exists secureboot &&" \
  413. "sf read $kernelheader_addr_r $kernelheader_start " \
  414. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  415. " bootm $load_addr#$board\0" \
  416. "nor_bootcmd=echo Trying load from nor..;" \
  417. "cp.b $kernel_addr $load_addr " \
  418. "$kernel_size ; env exists secureboot && " \
  419. "cp.b $kernelheader_addr $kernelheader_addr_r " \
  420. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  421. "bootm $load_addr#$board\0"
  422. #endif
  423. #ifdef CONFIG_TFABOOT
  424. #define QSPI_NOR_BOOTCOMMAND \
  425. "sf probe 0:0; " \
  426. "sf read 0x806c0000 0x6c0000 0x40000; " \
  427. "env exists mcinitcmd && env exists secureboot "\
  428. "&& esbc_validate 0x806c0000; " \
  429. "sf read 0x80d00000 0xd00000 0x100000; " \
  430. "env exists mcinitcmd && " \
  431. "fsl_mc lazyapply dpl 0x80d00000; " \
  432. "run distro_bootcmd;run qspi_bootcmd; " \
  433. "env exists secureboot && esbc_halt;"
  434. /* Try to boot an on-SD kernel first, then do normal distro boot */
  435. #define SD_BOOTCOMMAND \
  436. "env exists mcinitcmd && env exists secureboot "\
  437. "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
  438. "&& esbc_validate $load_addr; " \
  439. "env exists mcinitcmd && run mcinitcmd " \
  440. "&& mmc read 0x80d00000 0x6800 0x800 " \
  441. "&& fsl_mc lazyapply dpl 0x80d00000; " \
  442. "run distro_bootcmd;run sd_bootcmd; " \
  443. "env exists secureboot && esbc_halt;"
  444. /* Try to boot an on-NOR kernel first, then do normal distro boot */
  445. #define IFC_NOR_BOOTCOMMAND \
  446. "env exists mcinitcmd && env exists secureboot "\
  447. "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
  448. "&& fsl_mc lazyapply dpl 0x580d00000;" \
  449. "run distro_bootcmd;run nor_bootcmd; " \
  450. "env exists secureboot && esbc_halt;"
  451. #else
  452. #ifdef CONFIG_QSPI_BOOT
  453. /* Try to boot an on-QSPI kernel first, then do normal distro boot */
  454. #elif defined(CONFIG_SD_BOOT)
  455. /* Try to boot an on-SD kernel first, then do normal distro boot */
  456. #else
  457. /* Try to boot an on-NOR kernel first, then do normal distro boot */
  458. #endif
  459. #endif
  460. /* MAC/PHY configuration */
  461. #define CORTINA_PHY_ADDR1 0x10
  462. #define CORTINA_PHY_ADDR2 0x11
  463. #define CORTINA_PHY_ADDR3 0x12
  464. #define CORTINA_PHY_ADDR4 0x13
  465. #define AQ_PHY_ADDR1 0x00
  466. #define AQ_PHY_ADDR2 0x01
  467. #define AQ_PHY_ADDR3 0x02
  468. #define AQ_PHY_ADDR4 0x03
  469. #define AQR405_IRQ_MASK 0x36
  470. #define CONFIG_ETHPRIME "DPMAC1@xgmii"
  471. #include <asm/fsl_secure_boot.h>
  472. #endif /* __LS2_RDB_H */