ls1088a_common.h 5.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #ifndef __LS1088_COMMON_H
  6. #define __LS1088_COMMON_H
  7. /* SPL build */
  8. #ifdef CONFIG_SPL_BUILD
  9. #define SPL_NO_BOARDINFO
  10. #define SPL_NO_QIXIS
  11. #define SPL_NO_PCI
  12. #define SPL_NO_ENV
  13. #define SPL_NO_RTC
  14. #define SPL_NO_USB
  15. #define SPL_NO_SATA
  16. #define SPL_NO_QSPI
  17. #define SPL_NO_IFC
  18. #undef CONFIG_DISPLAY_CPUINFO
  19. #endif
  20. #include <asm/arch/stream_id_lsch3.h>
  21. #include <asm/arch/config.h>
  22. #include <asm/arch/soc.h>
  23. #define LS1088ARDB_PB_BOARD 0x4A
  24. /* Link Definitions */
  25. #ifdef CONFIG_TFABOOT
  26. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  27. #else
  28. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  29. #endif
  30. /* Link Definitions */
  31. #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
  32. #define CONFIG_VERY_BIG_RAM
  33. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  34. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  35. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  36. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
  37. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
  38. /*
  39. * SMP Definitinos
  40. */
  41. #define CPU_RELEASE_ADDR secondary_boot_addr
  42. /* GPIO */
  43. /* I2C */
  44. /* Serial Port */
  45. #define CONFIG_SYS_NS16550_SERIAL
  46. #define CONFIG_SYS_NS16550_REG_SIZE 1
  47. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  48. /*
  49. * During booting, IFC is mapped at the region of 0x30000000.
  50. * But this region is limited to 256MB. To accommodate NOR, promjet
  51. * and FPGA. This region is divided as below:
  52. * 0x30000000 - 0x37ffffff : 128MB : NOR flash
  53. * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
  54. * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
  55. *
  56. * To accommodate bigger NOR flash and other devices, we will map IFC
  57. * chip selects to as below:
  58. * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  59. * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
  60. * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  61. * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  62. * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  63. *
  64. * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
  65. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  66. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  67. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  68. * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  69. */
  70. #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
  71. #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
  72. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  73. #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
  74. #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
  75. #ifndef __ASSEMBLY__
  76. unsigned long long get_qixis_addr(void);
  77. #endif
  78. #define QIXIS_BASE get_qixis_addr()
  79. #define QIXIS_BASE_PHYS 0x20000000
  80. #define QIXIS_BASE_PHYS_EARLY 0xC000000
  81. #define CONFIG_SYS_NAND_BASE 0x530000000ULL
  82. #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
  83. /* MC firmware */
  84. /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
  85. #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
  86. #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
  87. #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
  88. #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
  89. #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
  90. #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
  91. /* Define phy_reset function to boot the MC based on mcinitcmd.
  92. * This happens late enough to properly fixup u-boot env MAC addresses.
  93. */
  94. #define CONFIG_RESET_PHY_R
  95. /*
  96. * Carve out a DDR region which will not be used by u-boot/Linux
  97. *
  98. * It will be used by MC and Debug Server. The MC region must be
  99. * 512MB aligned, so the min size to hide is 512MB.
  100. */
  101. #if defined(CONFIG_FSL_MC_ENET)
  102. #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
  103. #endif
  104. /* Miscellaneous configurable options */
  105. /* SATA */
  106. #ifdef CONFIG_SCSI
  107. #define CONFIG_SCSI_AHCI_PLAT
  108. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  109. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  110. #define CONFIG_SYS_SCSI_MAX_LUN 1
  111. #endif
  112. /* Physical Memory Map */
  113. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  114. #define CONFIG_HWCONFIG
  115. #define HWCONFIG_BUFFER_SIZE 128
  116. /* #define CONFIG_DISPLAY_CPUINFO */
  117. #ifndef SPL_NO_ENV
  118. /* Initial environment variables */
  119. #define CONFIG_EXTRA_ENV_SETTINGS \
  120. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  121. "loadaddr=0x80100000\0" \
  122. "kernel_addr=0x100000\0" \
  123. "ramdisk_addr=0x800000\0" \
  124. "ramdisk_size=0x2000000\0" \
  125. "fdt_high=0xa0000000\0" \
  126. "initrd_high=0xffffffffffffffff\0" \
  127. "kernel_start=0x581000000\0" \
  128. "kernel_load=0xa0000000\0" \
  129. "kernel_size=0x2800000\0" \
  130. "console=ttyAMA0,38400n8\0" \
  131. "mcinitcmd=fsl_mc start mc 0x580a00000" \
  132. " 0x580e00000 \0"
  133. #endif
  134. /* Monitor Command Prompt */
  135. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  136. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  137. sizeof(CONFIG_SYS_PROMPT) + 16)
  138. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
  139. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  140. #ifdef CONFIG_SPL
  141. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  142. #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
  143. #define CONFIG_SPL_MAX_SIZE 0x16000
  144. #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
  145. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  146. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
  147. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  148. #ifdef CONFIG_NXP_ESBC
  149. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  150. /*
  151. * HDR would be appended at end of image and copied to DDR along
  152. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  153. * size increases then increase this size in case of secure boot as
  154. * it uses raw u-boot image instead of fit image.
  155. */
  156. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  157. #else
  158. #define CONFIG_SYS_MONITOR_LEN 0x100000
  159. #endif /* ifdef CONFIG_NXP_ESBC */
  160. #endif
  161. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  162. #endif /* __LS1088_COMMON_H */