ls1046a_common.h 7.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor
  4. * Copyright 2019-2021 NXP
  5. */
  6. #ifndef __LS1046A_COMMON_H
  7. #define __LS1046A_COMMON_H
  8. /* SPL build */
  9. #ifdef CONFIG_SPL_BUILD
  10. #define SPL_NO_QBMAN
  11. #define SPL_NO_FMAN
  12. #define SPL_NO_ENV
  13. #define SPL_NO_MISC
  14. #define SPL_NO_QSPI
  15. #define SPL_NO_USB
  16. #define SPL_NO_SATA
  17. #endif
  18. #if defined(CONFIG_SPL_BUILD) && \
  19. (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
  20. #define SPL_NO_MMC
  21. #endif
  22. #if defined(CONFIG_SPL_BUILD) && \
  23. !defined(CONFIG_SPL_FSL_LS_PPA)
  24. #define SPL_NO_IFC
  25. #endif
  26. #include <asm/arch/config.h>
  27. #include <asm/arch/stream_id_lsch2.h>
  28. /* Link Definitions */
  29. #ifdef CONFIG_TFABOOT
  30. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
  31. #else
  32. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  33. #endif
  34. #define CONFIG_VERY_BIG_RAM
  35. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
  36. #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
  37. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  38. #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
  39. #define CPU_RELEASE_ADDR secondary_boot_addr
  40. /* Generic Timer Definitions */
  41. #define COUNTER_FREQUENCY 25000000 /* 25MHz */
  42. /* Serial Port */
  43. #define CONFIG_SYS_NS16550_SERIAL
  44. #define CONFIG_SYS_NS16550_REG_SIZE 1
  45. #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
  46. /* SD boot SPL */
  47. #ifdef CONFIG_SD_BOOT
  48. #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
  49. #define CONFIG_SPL_STACK 0x10020000
  50. #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
  51. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  52. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  53. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  54. CONFIG_SPL_BSS_MAX_SIZE)
  55. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  56. #ifdef CONFIG_NXP_ESBC
  57. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  58. /*
  59. * HDR would be appended at end of image and copied to DDR along
  60. * with U-Boot image. Here u-boot max. size is 512K. So if binary
  61. * size increases then increase this size in case of secure boot as
  62. * it uses raw u-boot image instead of fit image.
  63. */
  64. #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  65. #else
  66. #define CONFIG_SYS_MONITOR_LEN 0x100000
  67. #endif /* ifdef CONFIG_NXP_ESBC */
  68. #endif
  69. #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
  70. #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl"
  71. #define CONFIG_SPL_MAX_SIZE 0x1f000
  72. #define CONFIG_SPL_STACK 0x10020000
  73. #define CONFIG_SPL_PAD_TO 0x20000
  74. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  75. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  76. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  77. CONFIG_SPL_BSS_MAX_SIZE)
  78. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  79. #define CONFIG_SYS_MONITOR_LEN 0x100000
  80. #endif
  81. /* NAND SPL */
  82. #ifdef CONFIG_NAND_BOOT
  83. #define CONFIG_SPL_PBL_PAD
  84. #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
  85. #define CONFIG_SPL_STACK 0x1001f000
  86. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  87. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  88. #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
  89. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  90. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
  91. CONFIG_SPL_BSS_MAX_SIZE)
  92. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  93. #define CONFIG_SYS_MONITOR_LEN 0xa0000
  94. #endif
  95. /* GPIO */
  96. /* I2C */
  97. /* PCIe */
  98. #define CONFIG_PCIE1 /* PCIE controller 1 */
  99. #define CONFIG_PCIE2 /* PCIE controller 2 */
  100. #define CONFIG_PCIE3 /* PCIE controller 3 */
  101. #ifdef CONFIG_PCI
  102. #define CONFIG_PCI_SCAN_SHOW
  103. #endif
  104. /* SATA */
  105. #ifndef SPL_NO_SATA
  106. #define CONFIG_SCSI_AHCI_PLAT
  107. #define CONFIG_SYS_SATA AHCI_BASE_ADDR
  108. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  109. #define CONFIG_SYS_SCSI_MAX_LUN 1
  110. #endif
  111. /* FMan ucode */
  112. #ifndef SPL_NO_FMAN
  113. #define CONFIG_SYS_DPAA_FMAN
  114. #ifdef CONFIG_SYS_DPAA_FMAN
  115. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  116. #endif
  117. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  118. #endif
  119. /* Miscellaneous configurable options */
  120. #define CONFIG_HWCONFIG
  121. #define HWCONFIG_BUFFER_SIZE 128
  122. #ifndef CONFIG_SPL_BUILD
  123. #define BOOT_TARGET_DEVICES(func) \
  124. func(SCSI, scsi, 0) \
  125. func(MMC, mmc, 0) \
  126. func(USB, usb, 0) \
  127. func(DHCP, dhcp, na)
  128. #include <config_distro_bootcmd.h>
  129. #endif
  130. #if defined(CONFIG_TARGET_LS1046AFRWY)
  131. #define LS1046A_BOOT_SRC_AND_HDR\
  132. "boot_scripts=ls1046afrwy_boot.scr\0" \
  133. "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
  134. #elif defined(CONFIG_TARGET_LS1046AQDS)
  135. #define LS1046A_BOOT_SRC_AND_HDR\
  136. "boot_scripts=ls1046aqds_boot.scr\0" \
  137. "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
  138. #else
  139. #define LS1046A_BOOT_SRC_AND_HDR\
  140. "boot_scripts=ls1046ardb_boot.scr\0" \
  141. "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
  142. #endif
  143. #ifndef SPL_NO_MISC
  144. /* Initial environment variables */
  145. #define CONFIG_EXTRA_ENV_SETTINGS \
  146. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  147. "ramdisk_addr=0x800000\0" \
  148. "ramdisk_size=0x2000000\0" \
  149. "bootm_size=0x10000000\0" \
  150. "fdt_addr=0x64f00000\0" \
  151. "kernel_addr=0x61000000\0" \
  152. "scriptaddr=0x80000000\0" \
  153. "scripthdraddr=0x80080000\0" \
  154. "fdtheader_addr_r=0x80100000\0" \
  155. "kernelheader_addr_r=0x80200000\0" \
  156. "load_addr=0xa0000000\0" \
  157. "kernel_addr_r=0x81000000\0" \
  158. "fdt_addr_r=0x90000000\0" \
  159. "ramdisk_addr_r=0xa0000000\0" \
  160. "kernel_start=0x1000000\0" \
  161. "kernelheader_start=0x600000\0" \
  162. "kernel_load=0xa0000000\0" \
  163. "kernel_size=0x2800000\0" \
  164. "kernelheader_size=0x40000\0" \
  165. "kernel_addr_sd=0x8000\0" \
  166. "kernel_size_sd=0x14000\0" \
  167. "kernelhdr_addr_sd=0x3000\0" \
  168. "kernelhdr_size_sd=0x10\0" \
  169. "console=ttyS0,115200\0" \
  170. CONFIG_MTDPARTS_DEFAULT "\0" \
  171. BOOTENV \
  172. LS1046A_BOOT_SRC_AND_HDR \
  173. "scan_dev_for_boot_part=" \
  174. "part list ${devtype} ${devnum} devplist; " \
  175. "env exists devplist || setenv devplist 1; " \
  176. "for distro_bootpart in ${devplist}; do " \
  177. "if fstype ${devtype} " \
  178. "${devnum}:${distro_bootpart} " \
  179. "bootfstype; then " \
  180. "run scan_dev_for_boot; " \
  181. "fi; " \
  182. "done\0" \
  183. "boot_a_script=" \
  184. "load ${devtype} ${devnum}:${distro_bootpart} " \
  185. "${scriptaddr} ${prefix}${script}; " \
  186. "env exists secureboot && load ${devtype} " \
  187. "${devnum}:${distro_bootpart} " \
  188. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  189. "env exists secureboot " \
  190. "&& esbc_validate ${scripthdraddr};" \
  191. "source ${scriptaddr}\0" \
  192. "qspi_bootcmd=echo Trying load from qspi..;" \
  193. "sf probe && sf read $load_addr " \
  194. "$kernel_start $kernel_size; env exists secureboot " \
  195. "&& sf read $kernelheader_addr_r $kernelheader_start " \
  196. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  197. "bootm $load_addr#$board\0" \
  198. "nand_bootcmd=echo Trying load from nand..;" \
  199. "nand info; nand read $load_addr " \
  200. "$kernel_start $kernel_size; env exists secureboot " \
  201. "&& nand read $kernelheader_addr_r $kernelheader_start " \
  202. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  203. "bootm $load_addr#$board\0" \
  204. "nor_bootcmd=echo Trying load from nor..;" \
  205. "cp.b $kernel_addr $load_addr " \
  206. "$kernel_size; env exists secureboot " \
  207. "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
  208. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  209. "bootm $load_addr#$board\0" \
  210. "sd_bootcmd=echo Trying load from SD ..;" \
  211. "mmcinfo; mmc read $load_addr " \
  212. "$kernel_addr_sd $kernel_size_sd && " \
  213. "env exists secureboot && mmc read $kernelheader_addr_r " \
  214. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  215. " && esbc_validate ${kernelheader_addr_r};" \
  216. "bootm $load_addr#$board\0"
  217. #endif
  218. /* Monitor Command Prompt */
  219. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  220. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  221. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  222. #include <asm/arch/soc.h>
  223. #endif /* __LS1046A_COMMON_H */