ls1043ardb.h 7.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. */
  5. #ifndef __LS1043ARDB_H__
  6. #define __LS1043ARDB_H__
  7. #include "ls1043a_common.h"
  8. #define CONFIG_LAYERSCAPE_NS_ACCESS
  9. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  10. /* Physical Memory Map */
  11. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  12. #define CONFIG_SYS_SPD_BUS_NUM 0
  13. #ifndef CONFIG_SPL
  14. #define CONFIG_SYS_DDR_RAW_TIMING
  15. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  16. #endif
  17. #ifdef CONFIG_SD_BOOT
  18. #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
  19. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
  20. #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
  21. #endif
  22. /*
  23. * NOR Flash Definitions
  24. */
  25. #define CONFIG_SYS_NOR_CSPR_EXT (0x0)
  26. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  27. #define CONFIG_SYS_NOR_CSPR \
  28. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  29. CSPR_PORT_SIZE_16 | \
  30. CSPR_MSEL_NOR | \
  31. CSPR_V)
  32. /* NOR Flash Timing Params */
  33. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  34. CSOR_NOR_TRHZ_80)
  35. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
  36. FTIM0_NOR_TEADC(0x1) | \
  37. FTIM0_NOR_TAVDS(0x0) | \
  38. FTIM0_NOR_TEAHC(0xc))
  39. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
  40. FTIM1_NOR_TRAD_NOR(0xb) | \
  41. FTIM1_NOR_TSEQRAD_NOR(0x9))
  42. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
  43. FTIM2_NOR_TCH(0x4) | \
  44. FTIM2_NOR_TWPH(0x8) | \
  45. FTIM2_NOR_TWP(0x10))
  46. #define CONFIG_SYS_NOR_FTIM3 0
  47. #define CONFIG_SYS_IFC_CCR 0x01000000
  48. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  49. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  50. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  51. #define CONFIG_SYS_FLASH_EMPTY_INFO
  52. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
  53. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  54. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  55. /*
  56. * NAND Flash Definitions
  57. */
  58. #define CONFIG_SYS_NAND_BASE 0x7e800000
  59. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  60. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  61. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  62. | CSPR_PORT_SIZE_8 \
  63. | CSPR_MSEL_NAND \
  64. | CSPR_V)
  65. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  66. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  67. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  68. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  69. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  70. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  71. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  72. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  73. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  74. FTIM0_NAND_TWP(0x18) | \
  75. FTIM0_NAND_TWCHT(0x7) | \
  76. FTIM0_NAND_TWH(0xa))
  77. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  78. FTIM1_NAND_TWBE(0x39) | \
  79. FTIM1_NAND_TRR(0xe) | \
  80. FTIM1_NAND_TRP(0x18))
  81. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  82. FTIM2_NAND_TREH(0xa) | \
  83. FTIM2_NAND_TWHRE(0x1e))
  84. #define CONFIG_SYS_NAND_FTIM3 0x0
  85. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  86. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  87. #define CONFIG_MTD_NAND_VERIFY_WRITE
  88. #ifdef CONFIG_NAND_BOOT
  89. #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
  90. #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
  91. #endif
  92. /*
  93. * CPLD
  94. */
  95. #define CONFIG_SYS_CPLD_BASE 0x7fb00000
  96. #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  97. #define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
  98. #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  99. CSPR_PORT_SIZE_8 | \
  100. CSPR_MSEL_GPCM | \
  101. CSPR_V)
  102. #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
  103. #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  104. CSOR_NOR_NOR_MODE_AVD_NOR | \
  105. CSOR_NOR_TRHZ_80)
  106. /* CPLD Timing parameters for IFC GPCM */
  107. #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
  108. FTIM0_GPCM_TEADC(0xf) | \
  109. FTIM0_GPCM_TEAHC(0xf))
  110. #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  111. FTIM1_GPCM_TRAD(0x3f))
  112. #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  113. FTIM2_GPCM_TCH(0xf) | \
  114. FTIM2_GPCM_TWP(0xff))
  115. #define CONFIG_SYS_CPLD_FTIM3 0x0
  116. /* IFC Timing Params */
  117. #ifdef CONFIG_TFABOOT
  118. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  119. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  120. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  121. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  122. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  123. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  124. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  125. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  126. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  127. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  128. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  129. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  130. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  131. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  132. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  133. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  134. #else
  135. #ifdef CONFIG_NAND_BOOT
  136. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  137. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  138. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  139. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  140. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  141. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  142. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  143. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  144. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  145. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  146. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  147. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  148. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  149. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  150. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  151. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  152. #else
  153. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  154. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  155. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  156. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  157. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  158. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  159. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  160. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  161. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  162. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  163. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  164. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  165. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  166. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  167. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  168. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  169. #endif
  170. #endif
  171. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
  172. #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
  173. #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
  174. #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
  175. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
  176. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
  177. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
  178. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
  179. /* EEPROM */
  180. #ifndef SPL_NO_EEPROM
  181. #define CONFIG_SYS_I2C_EEPROM_NXID
  182. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  183. #endif
  184. /*
  185. * Environment
  186. */
  187. /* FMan */
  188. #ifndef SPL_NO_FMAN
  189. #define AQR105_IRQ_MASK 0x40000000
  190. #ifdef CONFIG_SYS_DPAA_FMAN
  191. #define RGMII_PHY1_ADDR 0x1
  192. #define RGMII_PHY2_ADDR 0x2
  193. #define QSGMII_PORT1_PHY_ADDR 0x4
  194. #define QSGMII_PORT2_PHY_ADDR 0x5
  195. #define QSGMII_PORT3_PHY_ADDR 0x6
  196. #define QSGMII_PORT4_PHY_ADDR 0x7
  197. #define FM1_10GEC1_PHY_ADDR 0x1
  198. #define CONFIG_ETHPRIME "FM1@DTSEC3"
  199. #endif
  200. #endif
  201. /* SATA */
  202. #ifndef SPL_NO_SATA
  203. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
  204. #define CONFIG_SYS_SCSI_MAX_LUN 2
  205. #define SCSI_VEND_ID 0x1b4b
  206. #define SCSI_DEV_ID 0x9170
  207. #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
  208. #endif
  209. #include <asm/fsl_secure_boot.h>
  210. #endif /* __LS1043ARDB_H__ */