ls1028aqds.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2019-2020 NXP
  4. */
  5. #ifndef __LS1028A_QDS_H
  6. #define __LS1028A_QDS_H
  7. #include "ls1028a_common.h"
  8. #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
  9. /* DDR */
  10. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  11. #define CONFIG_QIXIS_I2C_ACCESS
  12. /*
  13. * QIXIS Definitions
  14. */
  15. #define CONFIG_FSL_QIXIS
  16. #ifdef CONFIG_FSL_QIXIS
  17. #define QIXIS_BASE 0x7fb00000
  18. #define QIXIS_BASE_PHYS QIXIS_BASE
  19. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  20. #define QIXIS_LBMAP_SWITCH 1
  21. #define QIXIS_LBMAP_MASK 0x0f
  22. #define QIXIS_LBMAP_SHIFT 5
  23. #define QIXIS_LBMAP_DFLTBANK 0x00
  24. #define QIXIS_LBMAP_ALTBANK 0x00
  25. #define QIXIS_LBMAP_SD 0x00
  26. #define QIXIS_LBMAP_EMMC 0x00
  27. #define QIXIS_LBMAP_QSPI 0x00
  28. #define QIXIS_RCW_SRC_SD 0x8
  29. #define QIXIS_RCW_SRC_EMMC 0x9
  30. #define QIXIS_RCW_SRC_QSPI 0xf
  31. #define QIXIS_RST_CTL_RESET 0x31
  32. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  33. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  34. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  35. #define QIXIS_RST_FORCE_MEM 0x01
  36. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  37. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  38. CSPR_PORT_SIZE_8 | \
  39. CSPR_MSEL_GPCM | \
  40. CSPR_V)
  41. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  42. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  43. CSOR_NOR_NOR_MODE_AVD_NOR | \
  44. CSOR_NOR_TRHZ_80)
  45. #endif
  46. /* RTC */
  47. #define CONFIG_SYS_RTC_BUS_NUM 1
  48. #define I2C_MUX_CH_RTC 0xB
  49. /* Store environment at top of flash */
  50. #ifdef CONFIG_SPL_BUILD
  51. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  52. #else
  53. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  54. #endif
  55. /* LPUART */
  56. #ifdef CONFIG_LPUART
  57. #define CONFIG_LPUART_32B_REG
  58. #define CFG_LPUART_MUX_MASK 0xf0
  59. #define CFG_LPUART_EN 0xf0
  60. #endif
  61. /* SATA */
  62. #define CONFIG_SCSI_AHCI_PLAT
  63. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  64. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  65. #define CONFIG_SYS_SCSI_MAX_LUN 1
  66. #ifndef SPL_NO_ENV
  67. #undef CONFIG_EXTRA_ENV_SETTINGS
  68. #define CONFIG_EXTRA_ENV_SETTINGS \
  69. "board=ls1028aqds\0" \
  70. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  71. "ramdisk_addr=0x800000\0" \
  72. "ramdisk_size=0x2000000\0" \
  73. "fdt_addr=0x00f00000\0" \
  74. "kernel_addr=0x01000000\0" \
  75. "scriptaddr=0x80000000\0" \
  76. "scripthdraddr=0x80080000\0" \
  77. "fdtheader_addr_r=0x80100000\0" \
  78. "kernelheader_addr_r=0x80200000\0" \
  79. "load_addr=0xa0000000\0" \
  80. "kernel_addr_r=0x81000000\0" \
  81. "fdt_addr_r=0x90000000\0" \
  82. "fdt2_addr_r=0x90010000\0" \
  83. "ramdisk_addr_r=0xa0000000\0" \
  84. "kernel_start=0x1000000\0" \
  85. "kernelheader_start=0x600000\0" \
  86. "kernel_load=0xa0000000\0" \
  87. "kernel_size=0x2800000\0" \
  88. "kernelheader_size=0x40000\0" \
  89. "kernel_addr_sd=0x8000\0" \
  90. "kernel_size_sd=0x14000\0" \
  91. "kernelhdr_addr_sd=0x3000\0" \
  92. "kernelhdr_size_sd=0x10\0" \
  93. "console=ttyS0,115200\0" \
  94. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  95. BOOTENV \
  96. "boot_scripts=ls1028aqds_boot.scr\0" \
  97. "boot_script_hdr=hdr_ls1028aqds_bs.out\0" \
  98. "scan_dev_for_boot_part=" \
  99. "part list ${devtype} ${devnum} devplist; " \
  100. "env exists devplist || setenv devplist 1; " \
  101. "for distro_bootpart in ${devplist}; do " \
  102. "if fstype ${devtype} " \
  103. "${devnum}:${distro_bootpart} " \
  104. "bootfstype; then " \
  105. "run scan_dev_for_boot; " \
  106. "fi; " \
  107. "done\0" \
  108. "boot_a_script=" \
  109. "load ${devtype} ${devnum}:${distro_bootpart} " \
  110. "${scriptaddr} ${prefix}${script}; " \
  111. "env exists secureboot && load ${devtype} " \
  112. "${devnum}:${distro_bootpart} " \
  113. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  114. "&& esbc_validate ${scripthdraddr};" \
  115. "source ${scriptaddr}\0" \
  116. "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
  117. "sf probe 0:0 && sf read $load_addr " \
  118. "$kernel_start $kernel_size ; env exists secureboot &&" \
  119. "sf read $kernelheader_addr_r $kernelheader_start " \
  120. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  121. " bootm $load_addr#$board\0" \
  122. "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
  123. "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \
  124. "&& hdp load $load_addr 0x2000\0" \
  125. "sd_bootcmd=echo Trying load from SD ...;" \
  126. "mmc dev 0; mmcinfo; mmc read $load_addr " \
  127. "$kernel_addr_sd $kernel_size_sd && " \
  128. "env exists secureboot && mmc read $kernelheader_addr_r " \
  129. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  130. " && esbc_validate ${kernelheader_addr_r};" \
  131. "bootm $load_addr#$board\0" \
  132. "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \
  133. "mmc dev 0;mmcinfo; mmc read $load_addr 0x4a00 0x200 " \
  134. "&& hdp load $load_addr 0x2000\0" \
  135. "emmc_bootcmd=echo Trying load from EMMC ..;" \
  136. "mmc dev 1; mmcinfo; mmc read $load_addr " \
  137. "$kernel_addr_sd $kernel_size_sd && " \
  138. "env exists secureboot && mmc read $kernelheader_addr_r " \
  139. "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  140. " && esbc_validate ${kernelheader_addr_r};" \
  141. "bootm $load_addr#$board\0" \
  142. "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \
  143. "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
  144. "&& hdp load $load_addr 0x2000\0"
  145. #endif
  146. #endif /* __LS1028A_QDS_H */