ls1021aiot.h 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  9. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  10. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  11. /*
  12. * DDR: 800 MHz ( 1600 MT/s data rate )
  13. */
  14. #define DDR_SDRAM_CFG 0x470c0008
  15. #define DDR_CS0_BNDS 0x008000bf
  16. #define DDR_CS0_CONFIG 0x80014302
  17. #define DDR_TIMING_CFG_0 0x50550004
  18. #define DDR_TIMING_CFG_1 0xbcb38c56
  19. #define DDR_TIMING_CFG_2 0x0040d120
  20. #define DDR_TIMING_CFG_3 0x010e1000
  21. #define DDR_TIMING_CFG_4 0x00000001
  22. #define DDR_TIMING_CFG_5 0x03401400
  23. #define DDR_SDRAM_CFG_2 0x00401010
  24. #define DDR_SDRAM_MODE 0x00061c60
  25. #define DDR_SDRAM_MODE_2 0x00180000
  26. #define DDR_SDRAM_INTERVAL 0x18600618
  27. #define DDR_DDR_WRLVL_CNTL 0x8655f605
  28. #define DDR_DDR_WRLVL_CNTL_2 0x05060607
  29. #define DDR_DDR_WRLVL_CNTL_3 0x05050505
  30. #define DDR_DDR_CDR1 0x80040000
  31. #define DDR_DDR_CDR2 0x00000001
  32. #define DDR_SDRAM_CLK_CNTL 0x02000000
  33. #define DDR_DDR_ZQ_CNTL 0x89080600
  34. #define DDR_CS0_CONFIG_2 0
  35. #define DDR_SDRAM_CFG_MEM_EN 0x80000000
  36. #define SDRAM_CFG2_D_INIT 0x00000010
  37. #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
  38. #define SDRAM_CFG2_FRC_SR 0x80000000
  39. #define SDRAM_CFG_BI 0x00000001
  40. #ifdef CONFIG_SD_BOOT
  41. #define CONFIG_SPL_MAX_SIZE 0x1a000
  42. #define CONFIG_SPL_STACK 0x1001d000
  43. #define CONFIG_SPL_PAD_TO 0x1c000
  44. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  45. CONFIG_SYS_MONITOR_LEN)
  46. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  47. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  48. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  49. #define CONFIG_SYS_MONITOR_LEN 0x80000
  50. #endif
  51. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  52. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  53. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  54. /*
  55. * Serial Port
  56. */
  57. #define CONFIG_SYS_NS16550_SERIAL
  58. #define CONFIG_SYS_NS16550_REG_SIZE 1
  59. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  60. /*
  61. * I2C
  62. */
  63. /* EEPROM */
  64. #define CONFIG_SYS_I2C_EEPROM_NXID
  65. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  66. /*
  67. * MMC
  68. */
  69. /* SATA */
  70. #define CONFIG_SCSI_AHCI_PLAT
  71. #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
  72. #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
  73. #endif
  74. #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
  75. PCI_DEVICE_ID_FREESCALE_AHCI}
  76. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  77. #define CONFIG_SYS_SCSI_MAX_LUN 1
  78. /* SPI */
  79. /*
  80. * eTSEC
  81. */
  82. #ifdef CONFIG_TSEC_ENET
  83. #define CONFIG_MII_DEFAULT_TSEC 1
  84. #define CONFIG_TSEC1 1
  85. #define CONFIG_TSEC1_NAME "eTSEC1"
  86. #define CONFIG_TSEC2 1
  87. #define CONFIG_TSEC2_NAME "eTSEC2"
  88. #define TSEC1_PHY_ADDR 1
  89. #define TSEC2_PHY_ADDR 3
  90. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  91. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  92. #define TSEC1_PHYIDX 0
  93. #define TSEC2_PHYIDX 0
  94. #define CONFIG_ETHPRIME "eTSEC2"
  95. #define CONFIG_HAS_ETH0
  96. #define CONFIG_HAS_ETH1
  97. #define CONFIG_HAS_ETH2
  98. #endif
  99. /* PCIe */
  100. #define CONFIG_PCIE1 /* PCIE controler 1 */
  101. #define CONFIG_PCIE2 /* PCIE controler 2 */
  102. #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
  103. #ifdef CONFIG_PCI
  104. #define CONFIG_PCI_SCAN_SHOW
  105. #endif
  106. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  107. #define CONFIG_LAYERSCAPE_NS_ACCESS
  108. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  109. #define COUNTER_FREQUENCY 12500000
  110. #define CONFIG_HWCONFIG
  111. #define HWCONFIG_BUFFER_SIZE 256
  112. #define CONFIG_FSL_DEVICE_DISABLE
  113. #define CONFIG_EXTRA_ENV_SETTINGS \
  114. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  115. "initrd_high=0xffffffff\0"
  116. /*
  117. * Miscellaneous configurable options
  118. */
  119. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  120. #define CONFIG_LS102XA_STREAM_ID
  121. #define CONFIG_SYS_INIT_SP_OFFSET \
  122. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  123. #define CONFIG_SYS_INIT_SP_ADDR \
  124. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  125. #ifdef CONFIG_SPL_BUILD
  126. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  127. #else
  128. /* start of monitor */
  129. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  130. #endif
  131. #include <asm/fsl_secure_boot.h>
  132. #endif