config.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014, Freescale Semiconductor
  4. */
  5. #ifndef _ASM_ARMV7_LS102XA_CONFIG_
  6. #define _ASM_ARMV7_LS102XA_CONFIG_
  7. #define OCRAM_BASE_ADDR 0x10000000
  8. #define OCRAM_SIZE 0x00010000
  9. #define OCRAM_BASE_S_ADDR 0x10010000
  10. #define OCRAM_S_SIZE 0x00010000
  11. #define CONFIG_SYS_DCSRBAR 0x20000000
  12. #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
  13. #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
  14. #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
  15. #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
  16. #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
  17. #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
  18. #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
  19. #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
  20. #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
  21. #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
  22. #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
  23. #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
  24. #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
  25. #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
  26. #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
  27. #define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
  28. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
  29. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
  30. #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
  31. #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
  32. #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
  33. #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
  34. #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
  35. #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
  36. #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
  37. #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
  38. #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
  39. #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  40. #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
  41. #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
  42. #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
  43. #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
  44. #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
  45. #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
  46. #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
  47. #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
  48. #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
  49. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
  50. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
  51. #define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL
  52. #define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL
  53. #define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL
  54. #define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL
  55. #define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */
  56. /*
  57. * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
  58. * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
  59. */
  60. #define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \
  61. CONFIG_SYS_PCIE1_VIRT_ADDR)
  62. #define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
  63. CONFIG_SYS_PCIE2_VIRT_ADDR)
  64. /* SATA */
  65. #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
  66. #define CONFIG_SCSI_AHCI_PLAT
  67. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  68. #define CONFIG_SYS_SCSI_MAX_LUN 1
  69. #ifdef CONFIG_DDR_SPD
  70. #define CONFIG_VERY_BIG_RAM
  71. #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
  72. #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
  73. #endif
  74. #define CONFIG_SYS_FSL_IFC_BE
  75. #define CONFIG_SYS_FSL_ESDHC_BE
  76. #define CONFIG_SYS_FSL_WDOG_BE
  77. #define CONFIG_SYS_FSL_DSPI_BE
  78. #define CONFIG_SYS_FSL_DCU_BE
  79. #define CONFIG_SYS_FSL_SEC_MON_LE
  80. #define CONFIG_SYS_FSL_SFP_VER_3_2
  81. #define CONFIG_SYS_FSL_SFP_BE
  82. #define CONFIG_SYS_FSL_SRK_LE
  83. #define DCU_LAYER_MAX_NUM 16
  84. #ifdef CONFIG_ARCH_LS1021A
  85. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  86. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  87. #else
  88. #error SoC not defined
  89. #endif
  90. #define FSL_IFC_COMPAT "fsl,ifc"
  91. #define FSL_QSPI_COMPAT "fsl,ls1021a-qspi"
  92. #define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi"
  93. #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */