falcon.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board/renesas/falcon/falcon.c
  4. * This file is Falcon board support.
  5. *
  6. * Copyright (C) 2020 Renesas Electronics Corp.
  7. */
  8. #include <common.h>
  9. #include <asm/arch/rmobile.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <asm/mach-types.h>
  14. #include <asm/processor.h>
  15. #include <linux/errno.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #define CPGWPR 0xE6150000
  18. #define CPGWPCR 0xE6150004
  19. #define EXTAL_CLK 16666600u
  20. #define CNTCR_BASE 0xE6080000
  21. #define CNTFID0 (CNTCR_BASE + 0x020)
  22. #define CNTCR_EN BIT(0)
  23. static void init_generic_timer(void)
  24. {
  25. u32 freq;
  26. /* Set frequency data in CNTFID0 */
  27. freq = EXTAL_CLK;
  28. /* Update memory mapped and register based freqency */
  29. asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
  30. writel(freq, CNTFID0);
  31. /* Enable counter */
  32. setbits_le32(CNTCR_BASE, CNTCR_EN);
  33. }
  34. /* Distributor Registers */
  35. #define GICD_BASE 0xF1000000
  36. /* ReDistributor Registers for Control and Physical LPIs */
  37. #define GICR_LPI_BASE 0xF1060000
  38. #define GICR_WAKER 0x0014
  39. #define GICR_PWRR 0x0024
  40. #define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
  41. #define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
  42. /* ReDistributor Registers for SGIs and PPIs */
  43. #define GICR_SGI_BASE 0xF1070000
  44. #define GICR_IGROUPR0 0x0080
  45. static void init_gic_v3(void)
  46. {
  47. /* GIC v3 power on */
  48. writel(0x00000002, (GICR_LPI_PWRR));
  49. /* Wait till the WAKER_CA_BIT changes to 0 */
  50. writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER));
  51. while (readl(GICR_LPI_WAKER) & 0x00000004)
  52. ;
  53. writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
  54. }
  55. void s_init(void)
  56. {
  57. init_generic_timer();
  58. }
  59. int board_early_init_f(void)
  60. {
  61. /* Unlock CPG access */
  62. writel(0x5A5AFFFF, CPGWPR);
  63. writel(0xA5A50000, CPGWPCR);
  64. return 0;
  65. }
  66. int board_init(void)
  67. {
  68. /* address of boot parameters */
  69. gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
  70. init_gic_v3();
  71. return 0;
  72. }
  73. #define RST_BASE 0xE6160000 /* Domain0 */
  74. #define RST_SRESCR0 (RST_BASE + 0x18)
  75. #define RST_SPRES 0x5AA58000
  76. void reset_cpu(void)
  77. {
  78. writel(RST_SPRES, RST_SRESCR0);
  79. }