rcar-gen3-base.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
  4. *
  5. * Copyright (C) 2015 Renesas Electronics Corporation
  6. */
  7. #ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
  8. #define __ASM_ARCH_RCAR_GEN3_BASE_H
  9. /*
  10. * R-Car (R8A7750) I/O Addresses
  11. */
  12. #define RWDT_BASE 0xE6020000
  13. #define SWDT_BASE 0xE6030000
  14. #define LBSC_BASE 0xEE220200
  15. #define TMU_BASE 0xE61E0000
  16. #define GPIO5_BASE 0xE6055000
  17. /* SCIF */
  18. #define SCIF0_BASE 0xE6E60000
  19. #define SCIF1_BASE 0xE6E68000
  20. #define SCIF2_BASE 0xE6E88000
  21. #define SCIF3_BASE 0xE6C50000
  22. #define SCIF4_BASE 0xE6C40000
  23. #define SCIF5_BASE 0xE6F30000
  24. /* Module stop status register */
  25. #define MSTPSR0 0xE6150030
  26. #define MSTPSR1 0xE6150038
  27. #define MSTPSR2 0xE6150040
  28. #define MSTPSR3 0xE6150048
  29. #define MSTPSR4 0xE615004C
  30. #define MSTPSR5 0xE615003C
  31. #define MSTPSR6 0xE61501C0
  32. #define MSTPSR7 0xE61501C4
  33. #define MSTPSR8 0xE61509A0
  34. #define MSTPSR9 0xE61509A4
  35. #define MSTPSR10 0xE61509A8
  36. #define MSTPSR11 0xE61509AC
  37. /* Realtime module stop control register */
  38. #define RMSTPCR0 0xE6150110
  39. #define RMSTPCR1 0xE6150114
  40. #define RMSTPCR2 0xE6150118
  41. #define RMSTPCR3 0xE615011C
  42. #define RMSTPCR4 0xE6150120
  43. #define RMSTPCR5 0xE6150124
  44. #define RMSTPCR6 0xE6150128
  45. #define RMSTPCR7 0xE615012C
  46. #define RMSTPCR8 0xE6150980
  47. #define RMSTPCR9 0xE6150984
  48. #define RMSTPCR10 0xE6150988
  49. #define RMSTPCR11 0xE615098C
  50. /* System module stop control register */
  51. #define SMSTPCR0 0xE6150130
  52. #define SMSTPCR1 0xE6150134
  53. #define SMSTPCR2 0xE6150138
  54. #define SMSTPCR3 0xE615013C
  55. #define SMSTPCR4 0xE6150140
  56. #define SMSTPCR5 0xE6150144
  57. #define SMSTPCR6 0xE6150148
  58. #define SMSTPCR7 0xE615014C
  59. #define SMSTPCR8 0xE6150990
  60. #define SMSTPCR9 0xE6150994
  61. #define SMSTPCR10 0xE6150998
  62. #define SMSTPCR11 0xE615099C
  63. /* PFC */
  64. #define PFC_PUEN5 0xE6060414
  65. #define PUEN_SSI_SDATA4 BIT(17)
  66. #define PFC_PUEN6 0xE6060418
  67. #define PUEN_USB1_OVC (1 << 2)
  68. #define PUEN_USB1_PWEN (1 << 1)
  69. /* IICDVFS (I2C) */
  70. #define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000
  71. #ifndef __ASSEMBLY__
  72. #include <asm/types.h>
  73. #include <linux/bitops.h>
  74. /* RWDT */
  75. struct rcar_rwdt {
  76. u32 rwtcnt;
  77. u32 rwtcsra;
  78. u32 rwtcsrb;
  79. };
  80. /* SWDT */
  81. struct rcar_swdt {
  82. u32 swtcnt;
  83. u32 swtcsra;
  84. u32 swtcsrb;
  85. };
  86. #endif
  87. #endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */