abb.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Adaptive Body Bias programming sequence for OMAP family
  4. *
  5. * (C) Copyright 2013
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
  9. */
  10. #include <common.h>
  11. #include <asm/omap_common.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <linux/bitops.h>
  16. __weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
  17. {
  18. return -1;
  19. }
  20. static void abb_setup_timings(u32 setup)
  21. {
  22. u32 sys_rate, sr2_cnt, clk_cycles;
  23. /*
  24. * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
  25. * transition and must be programmed with the correct time at boot.
  26. * The value programmed into the register is the number of SYS_CLK
  27. * clock cycles that match a given wall time profiled for the ldo.
  28. * This value depends on:
  29. * settling time of ldo in micro-seconds (varies per OMAP family),
  30. * of clock cycles per SYS_CLK period (varies per OMAP family),
  31. * the SYS_CLK frequency in MHz (varies per board)
  32. * The formula is:
  33. *
  34. * ldo settling time (in micro-seconds)
  35. * SR2_WTCNT_VALUE = ------------------------------------------
  36. * (# system clock cycles) * (sys_clk period)
  37. *
  38. * Put another way:
  39. *
  40. * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
  41. *
  42. * To avoid dividing by zero multiply both "# clock cycles" and
  43. * "settling time" by 10 such that the final result is the one we want.
  44. */
  45. /* calculate SR2_WTCNT_VALUE */
  46. sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
  47. clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
  48. sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
  49. setbits_le32(setup,
  50. sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
  51. }
  52. void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
  53. u32 txdone, u32 txdone_mask, u32 opp)
  54. {
  55. u32 abb_type_mask, opp_sel_mask;
  56. /* sanity check */
  57. if (!setup || !control || !txdone)
  58. return;
  59. /* setup ABB only in case of Fast or Slow OPP */
  60. switch (opp) {
  61. case OMAP_ABB_FAST_OPP:
  62. abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK;
  63. opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK;
  64. break;
  65. case OMAP_ABB_SLOW_OPP:
  66. abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK;
  67. opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK;
  68. break;
  69. default:
  70. return;
  71. }
  72. /*
  73. * For some OMAP silicons additional setup for LDOVBB register is
  74. * required. This is determined by data retrieved from corresponding
  75. * OPP EFUSE register. Data, which is retrieved from EFUSE - is
  76. * ABB enable/disable flag and VSET value, which must be copied
  77. * to LDOVBB register. If function call fails - return quietly,
  78. * it means no ABB is required for such silicon.
  79. *
  80. * For silicons, which don't require LDOVBB setup "fuse" and
  81. * "ldovbb" offsets are not defined. ABB will be initialized in
  82. * the common way for them.
  83. */
  84. if (fuse && ldovbb) {
  85. if (abb_setup_ldovbb(fuse, ldovbb))
  86. return;
  87. }
  88. /* clear ABB registers */
  89. writel(0, setup);
  90. writel(0, control);
  91. /* configure timings, based on oscillator value */
  92. abb_setup_timings(setup);
  93. /* clear pending interrupts before setup */
  94. setbits_le32(txdone, txdone_mask);
  95. /* select ABB type */
  96. setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK);
  97. /* initiate ABB ldo change */
  98. setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK);
  99. /* wait until transition complete */
  100. if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY))
  101. puts("Error: ABB txdone is not set\n");
  102. /* clear ABB tranxdone */
  103. setbits_le32(txdone, txdone_mask);
  104. }