ctrl_pex.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include <common.h>
  6. #include <spl.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/cpu.h>
  9. #include <asm/arch/soc.h>
  10. #include <linux/bitops.h>
  11. #include <linux/delay.h>
  12. #include "ctrl_pex.h"
  13. #include "sys_env_lib.h"
  14. __weak void board_pex_config(void)
  15. {
  16. /* nothing in this weak default implementation */
  17. }
  18. int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
  19. {
  20. u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
  21. temp_reg, addr, dev_id, ctrl_mode;
  22. enum serdes_type serdes_type;
  23. u32 idx;
  24. DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
  25. for (idx = 0; idx < count; idx++) {
  26. serdes_type = serdes_map[idx].serdes_type;
  27. /* configuration for PEX only */
  28. if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
  29. (serdes_type != PEX2) && (serdes_type != PEX3))
  30. continue;
  31. if ((serdes_type != PEX0) &&
  32. ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  33. (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  34. /* for PEX by4 - relevant for the first port only */
  35. continue;
  36. }
  37. pex_idx = serdes_type - PEX0;
  38. tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx));
  39. tmp &= ~(0xf << 20);
  40. tmp |= (0x4 << 20);
  41. reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
  42. }
  43. tmp = reg_read(SOC_CTRL_REG);
  44. tmp &= ~0x03;
  45. for (idx = 0; idx < count; idx++) {
  46. serdes_type = serdes_map[idx].serdes_type;
  47. if ((serdes_type != PEX0) &&
  48. ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  49. (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  50. /* for PEX by4 - relevant for the first port only */
  51. continue;
  52. }
  53. switch (serdes_type) {
  54. case PEX0:
  55. tmp |= 0x1 << PCIE0_ENABLE_OFFS;
  56. break;
  57. case PEX1:
  58. tmp |= 0x1 << PCIE1_ENABLE_OFFS;
  59. break;
  60. case PEX2:
  61. tmp |= 0x1 << PCIE2_ENABLE_OFFS;
  62. break;
  63. case PEX3:
  64. tmp |= 0x1 << PCIE3_ENABLE_OFFS;
  65. break;
  66. default:
  67. break;
  68. }
  69. }
  70. reg_write(SOC_CTRL_REG, tmp);
  71. /* Support gen1/gen2 */
  72. DEBUG_INIT_FULL_S("Support gen1/gen2\n");
  73. board_pex_config();
  74. next_busno = 0;
  75. mdelay(150);
  76. for (idx = 0; idx < count; idx++) {
  77. serdes_type = serdes_map[idx].serdes_type;
  78. DEBUG_INIT_FULL_S(" serdes_type=0x");
  79. DEBUG_INIT_FULL_D(serdes_type, 8);
  80. DEBUG_INIT_FULL_S("\n");
  81. DEBUG_INIT_FULL_S(" idx=0x");
  82. DEBUG_INIT_FULL_D(idx, 8);
  83. DEBUG_INIT_FULL_S("\n");
  84. /* Configuration for PEX only */
  85. if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
  86. (serdes_type != PEX2) && (serdes_type != PEX3))
  87. continue;
  88. if ((serdes_type != PEX0) &&
  89. ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  90. (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  91. /* for PEX by4 - relevant for the first port only */
  92. continue;
  93. }
  94. pex_idx = serdes_type - PEX0;
  95. tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx));
  96. first_busno = next_busno;
  97. if ((tmp & 0x7f) != 0x7e) {
  98. DEBUG_INIT_S("PCIe, Idx ");
  99. DEBUG_INIT_D(pex_idx, 1);
  100. DEBUG_INIT_S(": detected no link\n");
  101. continue;
  102. }
  103. next_busno++;
  104. temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS
  105. (pex_idx, PEX_LINK_CAPABILITY_REG)));
  106. temp_pex_reg &= 0xf;
  107. if (temp_pex_reg != 0x2)
  108. continue;
  109. temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS(
  110. pex_idx,
  111. PEX_LINK_CTRL_STAT_REG)) &
  112. 0xf0000) >> 16;
  113. /* Check if the link established is GEN1 */
  114. DEBUG_INIT_FULL_S
  115. ("Checking if the link established is gen1\n");
  116. if (temp_reg != 0x1)
  117. continue;
  118. pex_local_bus_num_set(pex_idx, first_busno);
  119. pex_local_dev_num_set(pex_idx, 1);
  120. DEBUG_INIT_FULL_S("PCIe, Idx ");
  121. DEBUG_INIT_FULL_D(pex_idx, 1);
  122. DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n");
  123. /* link is Gen1, check the EP capability */
  124. addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff;
  125. DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4);
  126. if (addr == 0xff) {
  127. DEBUG_INIT_FULL_C
  128. ("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.",
  129. pex_idx, 1);
  130. continue;
  131. }
  132. while ((pex_config_read(pex_idx, first_busno, 0, 0, addr)
  133. & 0xff) != 0x10) {
  134. addr = (pex_config_read(pex_idx, first_busno, 0,
  135. 0, addr) & 0xff00) >> 8;
  136. }
  137. /* Check for Gen2 and above */
  138. if ((pex_config_read(pex_idx, first_busno, 0, 0,
  139. addr + 0xc) & 0xf) < 0x2) {
  140. DEBUG_INIT_S("PCIe, Idx ");
  141. DEBUG_INIT_D(pex_idx, 1);
  142. DEBUG_INIT_S(": remains Gen1\n");
  143. continue;
  144. }
  145. tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx));
  146. DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
  147. tmp &= ~(BIT(0) | BIT(1));
  148. tmp |= BIT(1);
  149. tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */
  150. reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
  151. DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
  152. tmp = reg_read(PEX_CTRL_REG(pex_idx));
  153. DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp);
  154. tmp |= BIT(10);
  155. reg_write(PEX_CTRL_REG(pex_idx), tmp);
  156. DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp);
  157. /*
  158. * We need to wait 10ms before reading the PEX_DBG_STATUS_REG
  159. * in order not to read the status of the former state
  160. */
  161. mdelay(10);
  162. DEBUG_INIT_S("PCIe, Idx ");
  163. DEBUG_INIT_D(pex_idx, 1);
  164. DEBUG_INIT_S
  165. (": Link upgraded to Gen2 based on client capabilities\n");
  166. }
  167. /* Update pex DEVICE ID */
  168. ctrl_mode = sys_env_model_get();
  169. for (idx = 0; idx < count; idx++) {
  170. serdes_type = serdes_map[idx].serdes_type;
  171. /* configuration for PEX only */
  172. if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
  173. (serdes_type != PEX2) && (serdes_type != PEX3))
  174. continue;
  175. if ((serdes_type != PEX0) &&
  176. ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  177. (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  178. /* for PEX by4 - relevant for the first port only */
  179. continue;
  180. }
  181. pex_idx = serdes_type - PEX0;
  182. dev_id = reg_read(PEX_CFG_DIRECT_ACCESS
  183. (pex_idx, PEX_DEVICE_AND_VENDOR_ID));
  184. dev_id &= 0xffff;
  185. dev_id |= ((ctrl_mode << 16) & 0xffff0000);
  186. reg_write(PEX_CFG_DIRECT_ACCESS
  187. (pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id);
  188. }
  189. DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4);
  190. return MV_OK;
  191. }
  192. int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
  193. {
  194. u32 pex_status;
  195. DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n");
  196. if (bus_num >= MAX_PEX_BUSSES) {
  197. DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n",
  198. bus_num, 4);
  199. return MV_BAD_PARAM;
  200. }
  201. pex_status = reg_read(PEX_STATUS_REG(pex_if));
  202. pex_status &= ~PXSR_PEX_BUS_NUM_MASK;
  203. pex_status |=
  204. (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
  205. reg_write(PEX_STATUS_REG(pex_if), pex_status);
  206. return MV_OK;
  207. }
  208. int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
  209. {
  210. u32 pex_status;
  211. DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n");
  212. pex_status = reg_read(PEX_STATUS_REG(pex_if));
  213. pex_status &= ~PXSR_PEX_DEV_NUM_MASK;
  214. pex_status |=
  215. (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
  216. reg_write(PEX_STATUS_REG(pex_if), pex_status);
  217. return MV_OK;
  218. }
  219. /*
  220. * pex_config_read - Read from configuration space
  221. *
  222. * DESCRIPTION:
  223. * This function performs a 32 bit read from PEX configuration space.
  224. * It supports both type 0 and type 1 of Configuration Transactions
  225. * (local and over bridge). In order to read from local bus segment, use
  226. * bus number retrieved from pex_local_bus_num_get(). Other bus numbers
  227. * will result configuration transaction of type 1 (over bridge).
  228. *
  229. * INPUT:
  230. * pex_if - PEX interface number.
  231. * bus - PEX segment bus number.
  232. * dev - PEX device number.
  233. * func - Function number.
  234. * reg_offs - Register offset.
  235. *
  236. * OUTPUT:
  237. * None.
  238. *
  239. * RETURN:
  240. * 32bit register data, 0xffffffff on error
  241. */
  242. u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off)
  243. {
  244. u32 pex_data = 0;
  245. u32 local_dev, local_bus;
  246. u32 pex_status;
  247. pex_status = reg_read(PEX_STATUS_REG(pex_if));
  248. local_dev =
  249. ((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
  250. local_bus =
  251. ((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
  252. /*
  253. * In PCI Express we have only one device number
  254. * and this number is the first number we encounter
  255. * else that the local_dev
  256. * spec pex define return on config read/write on any device
  257. */
  258. if (bus == local_bus) {
  259. if (local_dev == 0) {
  260. /*
  261. * if local dev is 0 then the first number we encounter
  262. * after 0 is 1
  263. */
  264. if ((dev != 1) && (dev != local_dev))
  265. return MV_ERROR;
  266. } else {
  267. /*
  268. * if local dev is not 0 then the first number we
  269. * encounter is 0
  270. */
  271. if ((dev != 0) && (dev != local_dev))
  272. return MV_ERROR;
  273. }
  274. }
  275. /* Creating PEX address to be passed */
  276. pex_data = (bus << PXCAR_BUS_NUM_OFFS);
  277. pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
  278. pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
  279. /* Legacy register space */
  280. pex_data |= (reg_off & PXCAR_REG_NUM_MASK);
  281. /* Extended register space */
  282. pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >>
  283. PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
  284. pex_data |= PXCAR_CONFIG_EN;
  285. /* Write the address to the PEX configuration address register */
  286. reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
  287. /*
  288. * In order to let the PEX controller absorbed the address
  289. * of the read transaction we perform a validity check that
  290. * the address was written
  291. */
  292. if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
  293. return MV_ERROR;
  294. /* Cleaning Master Abort */
  295. reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
  296. PXSAC_MABORT);
  297. /* Read the Data returned in the PEX Data register */
  298. pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
  299. DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
  300. return pex_data;
  301. }