cpu.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. * Copyright (C) 2020 Marek Behun <marek.behun@nic.cz>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <init.h>
  11. #include <linux/bitops.h>
  12. #include <linux/libfdt.h>
  13. #include <asm/io.h>
  14. #include <asm/system.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/armv8/mmu.h>
  18. #include <sort.h>
  19. /* Armada 3700 */
  20. #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
  21. #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
  22. #define MVEBU_XTAL_MODE_MASK BIT(9)
  23. #define MVEBU_XTAL_MODE_OFFS 9
  24. #define MVEBU_XTAL_CLOCK_25MHZ 0x0
  25. #define MVEBU_XTAL_CLOCK_40MHZ 0x1
  26. #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
  27. #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
  28. /* Armada 3700 CPU Address Decoder registers */
  29. #define MVEBU_CPU_DEC_WIN_REG_BASE (size_t)(MVEBU_REGISTER(0xcf00))
  30. #define MVEBU_CPU_DEC_WIN_CTRL(w) \
  31. (MVEBU_CPU_DEC_WIN_REG_BASE + ((w) << 4))
  32. #define MVEBU_CPU_DEC_WIN_CTRL_EN BIT(0)
  33. #define MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK 0xf
  34. #define MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS 4
  35. #define MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM 0
  36. #define MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE 2
  37. #define MVEBU_CPU_DEC_WIN_SIZE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x4)
  38. #define MVEBU_CPU_DEC_WIN_BASE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x8)
  39. #define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
  40. #define MVEBU_CPU_DEC_WIN_GRANULARITY 16
  41. #define MVEBU_CPU_DEC_WINS 5
  42. #define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2)
  43. #define A3700_PTE_BLOCK_NORMAL \
  44. (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
  45. #define A3700_PTE_BLOCK_DEVICE \
  46. (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)
  47. #define PCIE_PATH "/soc/pcie@d0070000"
  48. DECLARE_GLOBAL_DATA_PTR;
  49. static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
  50. {
  51. /*
  52. * SRAM, MMIO regions
  53. * Don't remove this, a3700_build_mem_map needs it.
  54. */
  55. .phys = SOC_REGS_PHY_BASE,
  56. .virt = SOC_REGS_PHY_BASE,
  57. .size = 0x02000000UL, /* 32MiB internal registers */
  58. .attrs = A3700_PTE_BLOCK_DEVICE
  59. },
  60. };
  61. struct mm_region *mem_map = mvebu_mem_map;
  62. static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size)
  63. {
  64. u32 reg;
  65. reg = readl(MVEBU_CPU_DEC_WIN_CTRL(win));
  66. if (!(reg & MVEBU_CPU_DEC_WIN_CTRL_EN))
  67. return -1;
  68. if (tgt) {
  69. reg >>= MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS;
  70. reg &= MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK;
  71. *tgt = reg;
  72. }
  73. if (base) {
  74. reg = readl(MVEBU_CPU_DEC_WIN_BASE(win));
  75. *base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY;
  76. }
  77. if (size) {
  78. /*
  79. * Window size is encoded as the number of 1s from LSB to MSB,
  80. * followed by 0s. The number of 1s specifies the size in 64 KiB
  81. * granularity.
  82. */
  83. reg = readl(MVEBU_CPU_DEC_WIN_SIZE(win));
  84. *size = ((reg + 1) << MVEBU_CPU_DEC_WIN_GRANULARITY);
  85. }
  86. return 0;
  87. }
  88. /*
  89. * Builds mem_map according to CPU Address Decoder settings, which were set by
  90. * the TIMH image on the Cortex-M3 secure processor, or by ARM Trusted Firmware
  91. */
  92. static void build_mem_map(void)
  93. {
  94. int win, region;
  95. region = 1;
  96. for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
  97. u32 base, tgt, size;
  98. u64 attrs;
  99. /* skip disabled windows */
  100. if (get_cpu_dec_win(win, &tgt, &base, &size))
  101. continue;
  102. if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
  103. attrs = A3700_PTE_BLOCK_NORMAL;
  104. else if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
  105. attrs = A3700_PTE_BLOCK_DEVICE;
  106. else
  107. /* skip windows with other targets */
  108. continue;
  109. mvebu_mem_map[region].phys = base;
  110. mvebu_mem_map[region].virt = base;
  111. mvebu_mem_map[region].size = size;
  112. mvebu_mem_map[region].attrs = attrs;
  113. ++region;
  114. }
  115. /* add list terminator */
  116. mvebu_mem_map[region].size = 0;
  117. mvebu_mem_map[region].attrs = 0;
  118. }
  119. void enable_caches(void)
  120. {
  121. build_mem_map();
  122. icache_enable();
  123. dcache_enable();
  124. }
  125. int a3700_dram_init(void)
  126. {
  127. int win;
  128. gd->ram_size = 0;
  129. for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
  130. u32 base, tgt, size;
  131. /* skip disabled windows */
  132. if (get_cpu_dec_win(win, &tgt, &base, &size))
  133. continue;
  134. /* skip non-DRAM windows */
  135. if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
  136. continue;
  137. /*
  138. * It is possible that one image was built for boards with
  139. * different RAM sizes, for example 512 MiB and 1 GiB.
  140. * We therefore try to determine the actual RAM size in the
  141. * window with get_ram_size.
  142. */
  143. gd->ram_size += get_ram_size((void *)(size_t)base, size);
  144. }
  145. return 0;
  146. }
  147. struct a3700_dram_window {
  148. size_t base, size;
  149. };
  150. static int dram_win_cmp(const void *a, const void *b)
  151. {
  152. size_t ab, bb;
  153. ab = ((const struct a3700_dram_window *)a)->base;
  154. bb = ((const struct a3700_dram_window *)b)->base;
  155. if (ab < bb)
  156. return -1;
  157. else if (ab > bb)
  158. return 1;
  159. else
  160. return 0;
  161. }
  162. int a3700_dram_init_banksize(void)
  163. {
  164. struct a3700_dram_window dram_wins[MVEBU_CPU_DEC_WINS];
  165. int bank, win, ndram_wins;
  166. u32 last_end;
  167. size_t size;
  168. ndram_wins = 0;
  169. for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
  170. u32 base, tgt, size;
  171. /* skip disabled windows */
  172. if (get_cpu_dec_win(win, &tgt, &base, &size))
  173. continue;
  174. /* skip non-DRAM windows */
  175. if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
  176. continue;
  177. dram_wins[win].base = base;
  178. dram_wins[win].size = size;
  179. ++ndram_wins;
  180. }
  181. qsort(dram_wins, ndram_wins, sizeof(dram_wins[0]), dram_win_cmp);
  182. bank = 0;
  183. last_end = -1;
  184. for (win = 0; win < ndram_wins; ++win) {
  185. /* again determining actual RAM size as in a3700_dram_init */
  186. size = get_ram_size((void *)dram_wins[win].base,
  187. dram_wins[win].size);
  188. /*
  189. * Check if previous window ends as the current starts. If yes,
  190. * merge these windows into one "bank". This is possible by this
  191. * simple check thanks to mem_map regions being qsorted in
  192. * build_mem_map.
  193. */
  194. if (last_end == dram_wins[win].base) {
  195. gd->bd->bi_dram[bank - 1].size += size;
  196. last_end += size;
  197. } else {
  198. if (bank == CONFIG_NR_DRAM_BANKS) {
  199. printf("Need more CONFIG_NR_DRAM_BANKS\n");
  200. return -ENOBUFS;
  201. }
  202. gd->bd->bi_dram[bank].start = dram_wins[win].base;
  203. gd->bd->bi_dram[bank].size = size;
  204. last_end = dram_wins[win].base + size;
  205. ++bank;
  206. }
  207. }
  208. /*
  209. * If there is more place for DRAM BANKS definitions than needed, fill
  210. * the rest with zeros.
  211. */
  212. for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
  213. gd->bd->bi_dram[bank].start = 0;
  214. gd->bd->bi_dram[bank].size = 0;
  215. }
  216. return 0;
  217. }
  218. static u32 find_pcie_window_base(void)
  219. {
  220. int win;
  221. for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
  222. u32 base, tgt;
  223. /* skip disabled windows */
  224. if (get_cpu_dec_win(win, &tgt, &base, NULL))
  225. continue;
  226. if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
  227. return base;
  228. }
  229. return -1;
  230. }
  231. int a3700_fdt_fix_pcie_regions(void *blob)
  232. {
  233. u32 new_ranges[14], base;
  234. const u32 *ranges;
  235. int node, len;
  236. node = fdt_path_offset(blob, PCIE_PATH);
  237. if (node < 0)
  238. return node;
  239. ranges = fdt_getprop(blob, node, "ranges", &len);
  240. if (!ranges)
  241. return -ENOENT;
  242. if (len != sizeof(new_ranges))
  243. return -EINVAL;
  244. memcpy(new_ranges, ranges, len);
  245. base = find_pcie_window_base();
  246. if (base == -1)
  247. return -ENOENT;
  248. new_ranges[2] = cpu_to_fdt32(base);
  249. new_ranges[4] = new_ranges[2];
  250. new_ranges[9] = cpu_to_fdt32(base + 0x1000000);
  251. new_ranges[11] = new_ranges[9];
  252. return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
  253. }
  254. void reset_cpu(ulong ignored)
  255. {
  256. /*
  257. * Write magic number of 0x1d1e to North Bridge Warm Reset register
  258. * to trigger warm reset
  259. */
  260. writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
  261. }
  262. /*
  263. * get_ref_clk
  264. *
  265. * return: reference clock in MHz (25 or 40)
  266. */
  267. u32 get_ref_clk(void)
  268. {
  269. u32 regval;
  270. regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
  271. MVEBU_XTAL_MODE_OFFS;
  272. if (regval == MVEBU_XTAL_CLOCK_25MHZ)
  273. return 25;
  274. else
  275. return 40;
  276. }