hardware.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Keystone2: Common SoC definitions, structures etc.
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #ifndef __ASM_ARCH_HARDWARE_H
  9. #define __ASM_ARCH_HARDWARE_H
  10. #include <config.h>
  11. #ifndef __ASSEMBLY__
  12. #include <linux/bitops.h>
  13. #include <linux/sizes.h>
  14. #include <asm/io.h>
  15. #define REG(addr) (*(volatile unsigned int *)(addr))
  16. #define REG_P(addr) ((volatile unsigned int *)(addr))
  17. typedef volatile unsigned int dv_reg;
  18. typedef volatile unsigned int *dv_reg_p;
  19. #endif
  20. #define KS2_DDRPHY_PIR_OFFSET 0x04
  21. #define KS2_DDRPHY_PGCR0_OFFSET 0x08
  22. #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
  23. #define KS2_DDRPHY_PGSR0_OFFSET 0x10
  24. #define KS2_DDRPHY_PGSR1_OFFSET 0x14
  25. #define KS2_DDRPHY_PLLCR_OFFSET 0x18
  26. #define KS2_DDRPHY_PTR0_OFFSET 0x1C
  27. #define KS2_DDRPHY_PTR1_OFFSET 0x20
  28. #define KS2_DDRPHY_PTR2_OFFSET 0x24
  29. #define KS2_DDRPHY_PTR3_OFFSET 0x28
  30. #define KS2_DDRPHY_PTR4_OFFSET 0x2C
  31. #define KS2_DDRPHY_DCR_OFFSET 0x44
  32. #define KS2_DDRPHY_DTPR0_OFFSET 0x48
  33. #define KS2_DDRPHY_DTPR1_OFFSET 0x4C
  34. #define KS2_DDRPHY_DTPR2_OFFSET 0x50
  35. #define KS2_DDRPHY_MR0_OFFSET 0x54
  36. #define KS2_DDRPHY_MR1_OFFSET 0x58
  37. #define KS2_DDRPHY_MR2_OFFSET 0x5C
  38. #define KS2_DDRPHY_DTCR_OFFSET 0x68
  39. #define KS2_DDRPHY_PGCR2_OFFSET 0x8C
  40. #define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
  41. #define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
  42. #define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
  43. #define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
  44. #define KS2_DDRPHY_DATX8_2_OFFSET 0x240
  45. #define KS2_DDRPHY_DATX8_3_OFFSET 0x280
  46. #define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0
  47. #define KS2_DDRPHY_DATX8_5_OFFSET 0x300
  48. #define KS2_DDRPHY_DATX8_6_OFFSET 0x340
  49. #define KS2_DDRPHY_DATX8_7_OFFSET 0x380
  50. #define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
  51. #define IODDRM_MASK 0x00000180
  52. #define ZCKSEL_MASK 0x01800000
  53. #define CL_MASK 0x00000072
  54. #define WR_MASK 0x00000E00
  55. #define BL_MASK 0x00000003
  56. #define RRMODE_MASK 0x00040000
  57. #define UDIMM_MASK 0x20000000
  58. #define BYTEMASK_MASK 0x0003FC00
  59. #define MPRDQ_MASK 0x00000080
  60. #define PDQ_MASK 0x00000070
  61. #define NOSRA_MASK 0x08000000
  62. #define ECC_MASK 0x00000001
  63. #define DXEN_MASK 0x00000001
  64. /* DDR3 definitions */
  65. #define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
  66. #define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
  67. #define KS2_DDR3A_DDRPHYC 0x02329000
  68. #define EMIF1_BASE KS2_DDR3A_EMIF_CTRL_BASE
  69. #define KS2_DDR3_MIDR_OFFSET 0x00
  70. #define KS2_DDR3_STATUS_OFFSET 0x04
  71. #define KS2_DDR3_SDCFG_OFFSET 0x08
  72. #define KS2_DDR3_SDRFC_OFFSET 0x10
  73. #define KS2_DDR3_SDTIM1_OFFSET 0x18
  74. #define KS2_DDR3_SDTIM2_OFFSET 0x1C
  75. #define KS2_DDR3_SDTIM3_OFFSET 0x20
  76. #define KS2_DDR3_SDTIM4_OFFSET 0x28
  77. #define KS2_DDR3_PMCTL_OFFSET 0x38
  78. #define KS2_DDR3_ZQCFG_OFFSET 0xC8
  79. #define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
  80. /* DDR3 ECC */
  81. #define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC
  82. #define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4
  83. #define KS2_DDR3_ECC_CTRL_OFFSET 0x110
  84. #define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114
  85. #define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130
  86. #define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C
  87. /* DDR3 ECC Interrupt Status register */
  88. #define KS2_DDR3_1B_ECC_ERR_SYS BIT(5)
  89. #define KS2_DDR3_2B_ECC_ERR_SYS BIT(4)
  90. #define KS2_DDR3_WR_ECC_ERR_SYS BIT(3)
  91. /* DDR3 ECC Control register */
  92. #define KS2_DDR3_ECC_EN BIT(31)
  93. #define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30)
  94. #define KS2_DDR3_ECC_VERIFY_EN BIT(29)
  95. #define KS2_DDR3_ECC_RMW_EN BIT(28)
  96. #define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0)
  97. #define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \
  98. KS2_DDR3_ECC_ADDR_RNG_PROT | \
  99. KS2_DDR3_ECC_VERIFY_EN)
  100. /* EDMA */
  101. #define KS2_EDMA0_BASE 0x02700000
  102. /* EDMA3 register offsets */
  103. #define KS2_EDMA_QCHMAP0 0x0200
  104. #define KS2_EDMA_IPR 0x1068
  105. #define KS2_EDMA_ICR 0x1070
  106. #define KS2_EDMA_QEECR 0x1088
  107. #define KS2_EDMA_QEESR 0x108c
  108. #define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
  109. /* NETCP pktdma */
  110. #ifdef CONFIG_SOC_K2G
  111. #define KS2_NETCP_PDMA_RX_FREE_QUEUE 113
  112. #define KS2_NETCP_PDMA_RX_RCV_QUEUE 114
  113. #else
  114. #define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
  115. #define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
  116. #endif
  117. /* Chip Interrupt Controller */
  118. #define KS2_CIC2_BASE 0x02608000
  119. /* Chip Interrupt Controller register offsets */
  120. #define KS2_CIC_CTRL 0x04
  121. #define KS2_CIC_HOST_CTRL 0x0C
  122. #define KS2_CIC_GLOBAL_ENABLE 0x10
  123. #define KS2_CIC_SYS_ENABLE_IDX_SET 0x28
  124. #define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
  125. #define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
  126. #define KS2_UART0_BASE 0x02530c00
  127. #define KS2_UART1_BASE 0x02531000
  128. /* Boot Config */
  129. #define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
  130. #define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
  131. #define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
  132. #define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
  133. #define KS2_ETHERNET_CFG (KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
  134. #define KS2_ETHERNET_RGMII 2
  135. /* PSC */
  136. #define KS2_PSC_BASE 0x02350000
  137. #define KS2_LPSC_GEM_0 15
  138. #define KS2_LPSC_TETRIS 52
  139. #define KS2_TETRIS_PWR_DOMAIN 31
  140. #define KS2_GEM_0_PWR_DOMAIN 8
  141. /* Chip configuration unlock codes and registers */
  142. #define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
  143. #define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
  144. #define KS2_KICK0_MAGIC 0x83e70b13
  145. #define KS2_KICK1_MAGIC 0x95a4f1e0
  146. /* PLL control registers */
  147. #define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
  148. #define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
  149. #define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
  150. #define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
  151. #define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
  152. #define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
  153. #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
  154. #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
  155. #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
  156. #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
  157. #define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390)
  158. #define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394)
  159. #define KS2_PLL_CNTRL_BASE 0x02310000
  160. #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
  161. #define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
  162. #define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
  163. #define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec)
  164. #define KS2_RSTCTRL_KEY 0x5a69
  165. #define KS2_RSTCTRL_MASK 0xffff0000
  166. #define KS2_RSTCTRL_SWRST 0xfffe0000
  167. #define KS2_RSTYPE_PLL_SOFT BIT(13)
  168. /* SPI */
  169. #ifdef CONFIG_SOC_K2G
  170. #define KS2_SPI0_BASE 0x21805400
  171. #define KS2_SPI1_BASE 0x21805800
  172. #define KS2_SPI2_BASE 0x21805c00
  173. #define KS2_SPI3_BASE 0x21806000
  174. #else
  175. #define KS2_SPI0_BASE 0x21000400
  176. #define KS2_SPI1_BASE 0x21000600
  177. #define KS2_SPI2_BASE 0x21000800
  178. #define KS2_SPI_BASE KS2_SPI0_BASE
  179. #endif
  180. /* AEMIF */
  181. #define KS2_AEMIF_CNTRL_BASE 0x21000a00
  182. #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
  183. /* Flag from ks2_debug options to check if DSPs need to stay ON */
  184. #define DBG_LEAVE_DSPS_ON 0x1
  185. /* MSMC control */
  186. #define KS2_MSMC_CTRL_BASE 0x0bc00000
  187. #define KS2_MSMC_DATA_BASE 0x0c000000
  188. /* KS2 Generic Privilege ID Settings for MSMC2 */
  189. #define KS2_MSMC_SEGMENT_C6X_0 0
  190. #define KS2_MSMC_SEGMENT_C6X_1 1
  191. #define KS2_MSMC_SEGMENT_C6X_2 2
  192. #define KS2_MSMC_SEGMENT_C6X_3 3
  193. #define KS2_MSMC_SEGMENT_C6X_4 4
  194. #define KS2_MSMC_SEGMENT_C6X_5 5
  195. #define KS2_MSMC_SEGMENT_C6X_6 6
  196. #define KS2_MSMC_SEGMENT_C6X_7 7
  197. #define KS2_MSMC_SEGMENT_DEBUG 12
  198. /* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */
  199. #define K2HKLE_MSMC_SEGMENT_ARM 8
  200. #define K2HKLE_MSMC_SEGMENT_NETCP 9
  201. #define K2HKLE_MSMC_SEGMENT_QM_PDSP 10
  202. #define K2HKLE_MSMC_SEGMENT_PCIE0 11
  203. /* K2HK specific Privilege ID Settings */
  204. #define K2HKE_MSMC_SEGMENT_HYPERLINK 14
  205. /* K2L specific Privilege ID Settings */
  206. #define K2L_MSMC_SEGMENT_PCIE1 14
  207. /* K2E specific Privilege ID Settings */
  208. #define K2E_MSMC_SEGMENT_PCIE1 13
  209. #define K2E_MSMC_SEGMENT_TSIP 15
  210. /* K2G specific Privilege ID Settings */
  211. #define K2G_MSMC_SEGMENT_ARM 1
  212. #define K2G_MSMC_SEGMENT_ICSS0 2
  213. #define K2G_MSMC_SEGMENT_ICSS1 3
  214. #define K2G_MSMC_SEGMENT_NSS 4
  215. #define K2G_MSMC_SEGMENT_PCIE 5
  216. #define K2G_MSMC_SEGMENT_USB 6
  217. #define K2G_MSMC_SEGMENT_MLB 8
  218. #define K2G_MSMC_SEGMENT_PMMC 9
  219. #define K2G_MSMC_SEGMENT_DSS 10
  220. #define K2G_MSMC_SEGMENT_MMC 11
  221. /* MSMC segment size shift bits */
  222. #define KS2_MSMC_SEG_SIZE_SHIFT 12
  223. #define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
  224. #define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
  225. KS2_MSMC_SEG_SIZE_SHIFT)
  226. /* Device speed */
  227. #define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
  228. #define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
  229. #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
  230. /* Queue manager */
  231. #ifdef CONFIG_SOC_K2G
  232. #define KS2_QM_BASE_ADDRESS 0x040C0000
  233. #define KS2_QM_CONF_BASE 0x04040000
  234. #define KS2_QM_DESC_SETUP_BASE 0x04080000
  235. #define KS2_QM_STATUS_RAM_BASE 0x0 /* K2G doesn't have it */
  236. #define KS2_QM_INTD_CONF_BASE 0x0
  237. #define KS2_QM_PDSP1_CMD_BASE 0x0
  238. #define KS2_QM_PDSP1_CTRL_BASE 0x0
  239. #define KS2_QM_PDSP1_IRAM_BASE 0x0
  240. #define KS2_QM_MANAGER_QUEUES_BASE 0x040c0000
  241. #define KS2_QM_MANAGER_Q_PROXY_BASE 0x04040200
  242. #define KS2_QM_QUEUE_STATUS_BASE 0x04100000
  243. #define KS2_QM_LINK_RAM_BASE 0x04020000
  244. #define KS2_QM_REGION_NUM 8
  245. #define KS2_QM_QPOOL_NUM 112
  246. #else
  247. #define KS2_QM_BASE_ADDRESS 0x23a80000
  248. #define KS2_QM_CONF_BASE 0x02a02000
  249. #define KS2_QM_DESC_SETUP_BASE 0x02a03000
  250. #define KS2_QM_STATUS_RAM_BASE 0x02a06000
  251. #define KS2_QM_INTD_CONF_BASE 0x02a0c000
  252. #define KS2_QM_PDSP1_CMD_BASE 0x02a20000
  253. #define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000
  254. #define KS2_QM_PDSP1_IRAM_BASE 0x02a10000
  255. #define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000
  256. #define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
  257. #define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
  258. #define KS2_QM_LINK_RAM_BASE 0x00100000
  259. #define KS2_QM_REGION_NUM 64
  260. #define KS2_QM_QPOOL_NUM 4000
  261. #endif
  262. /* USB */
  263. #define KS2_USB_SS_BASE 0x02680000
  264. #define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000)
  265. #define KS2_DEV_USB_PHY_BASE 0x02620738
  266. #define KS2_USB_PHY_CFG_BASE 0x02630000
  267. #define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
  268. /* SGMII SerDes */
  269. #define KS2_SGMII_SERDES_BASE 0x0232a000
  270. /* JTAG ID register */
  271. #define JTAGID_VARIANT_SHIFT 28
  272. #define JTAGID_VARIANT_MASK (0xf << 28)
  273. #define JTAGID_PART_NUM_SHIFT 12
  274. #define JTAGID_PART_NUM_MASK (0xffff << 12)
  275. /* PART NUMBER definitions */
  276. #define CPU_66AK2Hx 0xb981
  277. #define CPU_66AK2Ex 0xb9a6
  278. #define CPU_66AK2Lx 0xb9a7
  279. #define CPU_66AK2Gx 0xbb06
  280. /* Variant definitions */
  281. #define CPU_66AK2G1x 0x08
  282. /* DEVSPEED register */
  283. #define DEVSPEED_DEVSPEED_SHIFT 16
  284. #define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
  285. #define DEVSPEED_ARMSPEED_SHIFT 0
  286. #define DEVSPEED_ARMSPEED_MASK 0xfff
  287. #define DEVSPEED_NUMSPDS 12
  288. #ifdef CONFIG_SOC_K2HK
  289. #include <asm/arch/hardware-k2hk.h>
  290. #endif
  291. #ifdef CONFIG_SOC_K2E
  292. #include <asm/arch/hardware-k2e.h>
  293. #endif
  294. #ifdef CONFIG_SOC_K2L
  295. #include <asm/arch/hardware-k2l.h>
  296. #endif
  297. #ifdef CONFIG_SOC_K2G
  298. #include <asm/arch/hardware-k2g.h>
  299. #endif
  300. #ifndef __ASSEMBLY__
  301. static inline u16 get_part_number(void)
  302. {
  303. u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
  304. return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
  305. }
  306. static inline u8 cpu_is_k2hk(void)
  307. {
  308. return get_part_number() == CPU_66AK2Hx;
  309. }
  310. static inline u8 cpu_is_k2e(void)
  311. {
  312. return get_part_number() == CPU_66AK2Ex;
  313. }
  314. static inline u8 cpu_is_k2l(void)
  315. {
  316. return get_part_number() == CPU_66AK2Lx;
  317. }
  318. static inline u8 cpu_is_k2g(void)
  319. {
  320. return get_part_number() == CPU_66AK2Gx;
  321. }
  322. static inline u8 cpu_revision(void)
  323. {
  324. u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
  325. u8 rev = (jtag_id & JTAGID_VARIANT_MASK) >> JTAGID_VARIANT_SHIFT;
  326. return rev;
  327. }
  328. int cpu_to_bus(u32 *ptr, u32 length);
  329. void sdelay(unsigned long);
  330. #endif
  331. #endif /* __ASM_ARCH_HARDWARE_H */