hardware-k2hk.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * K2HK: SoC definitions
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #ifndef __ASM_ARCH_HARDWARE_K2HK_H
  9. #define __ASM_ARCH_HARDWARE_K2HK_H
  10. #ifndef __ASSEMBLY__
  11. #include <linux/bitops.h>
  12. #endif
  13. #define KS2_ARM_PLL_EN BIT(13)
  14. /* PA SS Registers */
  15. #define KS2_PASS_BASE 0x02000000
  16. /* Power and Sleep Controller (PSC) Domains */
  17. #define KS2_LPSC_MOD 0
  18. #define KS2_LPSC_DUMMY1 1
  19. #define KS2_LPSC_USB 2
  20. #define KS2_LPSC_EMIF25_SPI 3
  21. #define KS2_LPSC_TSIP 4
  22. #define KS2_LPSC_DEBUGSS_TRC 5
  23. #define KS2_LPSC_TETB_TRC 6
  24. #define KS2_LPSC_PKTPROC 7
  25. #define KS2_LPSC_PA KS2_LPSC_PKTPROC
  26. #define KS2_LPSC_SGMII 8
  27. #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
  28. #define KS2_LPSC_CRYPTO 9
  29. #define KS2_LPSC_PCIE 10
  30. #define KS2_LPSC_SRIO 11
  31. #define KS2_LPSC_VUSR0 12
  32. #define KS2_LPSC_CHIP_SRSS 13
  33. #define KS2_LPSC_MSMC 14
  34. #define KS2_LPSC_GEM_1 16
  35. #define KS2_LPSC_GEM_2 17
  36. #define KS2_LPSC_GEM_3 18
  37. #define KS2_LPSC_GEM_4 19
  38. #define KS2_LPSC_GEM_5 20
  39. #define KS2_LPSC_GEM_6 21
  40. #define KS2_LPSC_GEM_7 22
  41. #define KS2_LPSC_EMIF4F_DDR3A 23
  42. #define KS2_LPSC_EMIF4F_DDR3B 24
  43. #define KS2_LPSC_TAC 25
  44. #define KS2_LPSC_RAC 26
  45. #define KS2_LPSC_RAC_1 27
  46. #define KS2_LPSC_FFTC_A 28
  47. #define KS2_LPSC_FFTC_B 29
  48. #define KS2_LPSC_FFTC_C 30
  49. #define KS2_LPSC_FFTC_D 31
  50. #define KS2_LPSC_FFTC_E 32
  51. #define KS2_LPSC_FFTC_F 33
  52. #define KS2_LPSC_AI2 34
  53. #define KS2_LPSC_TCP3D_0 35
  54. #define KS2_LPSC_TCP3D_1 36
  55. #define KS2_LPSC_TCP3D_2 37
  56. #define KS2_LPSC_TCP3D_3 38
  57. #define KS2_LPSC_VCP2X4_A 39
  58. #define KS2_LPSC_CP2X4_B 40
  59. #define KS2_LPSC_VCP2X4_C 41
  60. #define KS2_LPSC_VCP2X4_D 42
  61. #define KS2_LPSC_VCP2X4_E 43
  62. #define KS2_LPSC_VCP2X4_F 44
  63. #define KS2_LPSC_VCP2X4_G 45
  64. #define KS2_LPSC_VCP2X4_H 46
  65. #define KS2_LPSC_BCP 47
  66. #define KS2_LPSC_DXB 48
  67. #define KS2_LPSC_VUSR1 49
  68. #define KS2_LPSC_XGE 50
  69. #define KS2_LPSC_ARM_SREFLEX 51
  70. /* DDR3B definitions */
  71. #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
  72. #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
  73. #define KS2_DDR3B_DDRPHYC 0x02328000
  74. #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */
  75. #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2
  76. channel 29 */
  77. /* SGMII SerDes */
  78. #define KS2_LANES_PER_SGMII_SERDES 4
  79. /* Number of DSP cores */
  80. #define KS2_NUM_DSPS 8
  81. /* NETCP pktdma */
  82. #define KS2_NETCP_PDMA_CTRL_BASE 0x02004000
  83. #define KS2_NETCP_PDMA_TX_BASE 0x02004400
  84. #define KS2_NETCP_PDMA_TX_CH_NUM 9
  85. #define KS2_NETCP_PDMA_RX_BASE 0x02004800
  86. #define KS2_NETCP_PDMA_RX_CH_NUM 26
  87. #define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00
  88. #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000
  89. #define KS2_NETCP_PDMA_RX_FLOW_NUM 32
  90. #define KS2_NETCP_PDMA_TX_SND_QUEUE 648
  91. /* NETCP */
  92. #define KS2_NETCP_BASE 0x02000000
  93. #endif /* __ASM_ARCH_HARDWARE_H */