clock_defs.h 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * keystone2: common pll clock definitions
  4. * (C) Copyright 2012-2014
  5. * Texas Instruments Incorporated, <www.ti.com>
  6. */
  7. #ifndef _CLOCK_DEFS_H_
  8. #define _CLOCK_DEFS_H_
  9. #include <asm/arch/hardware.h>
  10. #ifndef __ASSEMBLY__
  11. #include <linux/bitops.h>
  12. #endif
  13. /* PLL Control Registers */
  14. struct pllctl_regs {
  15. u32 ctl; /* 00 */
  16. u32 ocsel; /* 04 */
  17. u32 secctl; /* 08 */
  18. u32 resv0;
  19. u32 mult; /* 10 */
  20. u32 prediv; /* 14 */
  21. u32 div1; /* 18 */
  22. u32 div2; /* 1c */
  23. u32 div3; /* 20 */
  24. u32 oscdiv1; /* 24 */
  25. u32 resv1; /* 28 */
  26. u32 bpdiv; /* 2c */
  27. u32 wakeup; /* 30 */
  28. u32 resv2;
  29. u32 cmd; /* 38 */
  30. u32 stat; /* 3c */
  31. u32 alnctl; /* 40 */
  32. u32 dchange; /* 44 */
  33. u32 cken; /* 48 */
  34. u32 ckstat; /* 4c */
  35. u32 systat; /* 50 */
  36. u32 ckctl; /* 54 */
  37. u32 resv3[2];
  38. u32 div4; /* 60 */
  39. u32 div5; /* 64 */
  40. u32 div6; /* 68 */
  41. u32 div7; /* 6c */
  42. u32 div8; /* 70 */
  43. u32 div9; /* 74 */
  44. u32 div10; /* 78 */
  45. u32 div11; /* 7c */
  46. u32 div12; /* 80 */
  47. };
  48. static struct pllctl_regs *pllctl_regs[] = {
  49. (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
  50. };
  51. #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
  52. #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
  53. #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
  54. #define pllctl_reg_rmw(pll, reg, mask, val) \
  55. pllctl_reg_write(pll, reg, \
  56. (pllctl_reg_read(pll, reg) & ~(mask)) | val)
  57. #define pllctl_reg_setbits(pll, reg, mask) \
  58. pllctl_reg_rmw(pll, reg, 0, mask)
  59. #define pllctl_reg_clrbits(pll, reg, mask) \
  60. pllctl_reg_rmw(pll, reg, mask, 0)
  61. #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
  62. /* PLLCTL Bits */
  63. #define PLLCTL_PLLENSRC_SHIF 5
  64. #define PLLCTL_PLLENSRC_MASK BIT(5)
  65. #define PLLCTL_PLLRST_SHIFT 3
  66. #define PLLCTL_PLLRST_MASK BIT(3)
  67. #define PLLCTL_PLLPWRDN_SHIFT 1
  68. #define PLLCTL_PLLPWRDN_MASK BIT(1)
  69. #define PLLCTL_PLLEN_SHIFT 0
  70. #define PLLCTL_PLLEN_MASK BIT(0)
  71. /* SECCTL Bits */
  72. #define SECCTL_BYPASS_SHIFT 23
  73. #define SECCTL_BYPASS_MASK BIT(23)
  74. #define SECCTL_OP_DIV_SHIFT 19
  75. #define SECCTL_OP_DIV_MASK (0xf << 19)
  76. /* PLLM Bits */
  77. #define PLLM_MULT_LO_SHIFT 0
  78. #define PLLM_MULT_LO_MASK 0x3f
  79. #define PLLM_MULT_LO_BITS 6
  80. /* PLLDIVn Bits */
  81. #define PLLDIV_ENABLE_SHIFT 15
  82. #define PLLDIV_ENABLE_MASK BIT(15)
  83. #define PLLDIV_RATIO_SHIFT 0x0
  84. #define PLLDIV_RATIO_MASK 0xff
  85. #define PLLDIV_MAX 16
  86. /* PLLCMD Bits */
  87. #define PLLCMD_GOSET_SHIFT 0
  88. #define PLLCMD_GOSET_MASK BIT(0)
  89. /* PLLSTAT Bits */
  90. #define PLLSTAT_GOSTAT_SHIFT 0
  91. #define PLLSTAT_GOSTAT_MASK BIT(0)
  92. /* Device Config PLLCTL0 */
  93. #define CFG_PLLCTL0_BWADJ_SHIFT 24
  94. #define CFG_PLLCTL0_BWADJ_MASK (0xff << 24)
  95. #define CFG_PLLCTL0_BWADJ_BITS 8
  96. #define CFG_PLLCTL0_BYPASS_SHIFT 23
  97. #define CFG_PLLCTL0_BYPASS_MASK BIT(23)
  98. #define CFG_PLLCTL0_CLKOD_SHIFT 19
  99. #define CFG_PLLCTL0_CLKOD_MASK (0xf << 19)
  100. #define CFG_PLLCTL0_PLLM_HI_SHIFT 12
  101. #define CFG_PLLCTL0_PLLM_HI_MASK (0x7f << 12)
  102. #define CFG_PLLCTL0_PLLM_SHIFT 6
  103. #define CFG_PLLCTL0_PLLM_MASK (0x1fff << 6)
  104. #define CFG_PLLCTL0_PLLD_SHIFT 0
  105. #define CFG_PLLCTL0_PLLD_MASK 0x3f
  106. /* Device Config PLLCTL1 */
  107. #define CFG_PLLCTL1_RST_SHIFT 14
  108. #define CFG_PLLCTL1_RST_MASK BIT(14)
  109. #define CFG_PLLCTL1_PAPLL_SHIFT 13
  110. #define CFG_PLLCTL1_PAPLL_MASK BIT(13)
  111. #define CFG_PLLCTL1_ENSAT_SHIFT 6
  112. #define CFG_PLLCTL1_ENSAT_MASK BIT(6)
  113. #define CFG_PLLCTL1_BWADJ_SHIFT 0
  114. #define CFG_PLLCTL1_BWADJ_MASK 0xf
  115. #define MISC_CTL1_ARM_PLL_EN BIT(13)
  116. #endif /* _CLOCK_DEFS_H_ */