soc.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/mach-imx/hab.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/syscounter.h>
  18. #include <asm/armv8/mmu.h>
  19. #include <dm/uclass.h>
  20. #include <errno.h>
  21. #include <fdt_support.h>
  22. #include <fsl_wdog.h>
  23. #include <imx_sip.h>
  24. #include <linux/bitops.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #if defined(CONFIG_IMX_HAB)
  27. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  28. .bank = 1,
  29. .word = 3,
  30. };
  31. #endif
  32. int timer_init(void)
  33. {
  34. #ifdef CONFIG_SPL_BUILD
  35. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  36. unsigned long freq = readl(&sctr->cntfid0);
  37. /* Update with accurate clock frequency */
  38. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  39. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  40. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  41. #endif
  42. gd->arch.tbl = 0;
  43. gd->arch.tbu = 0;
  44. return 0;
  45. }
  46. void enable_tzc380(void)
  47. {
  48. struct iomuxc_gpr_base_regs *gpr =
  49. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  50. /* Enable TZASC and lock setting */
  51. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  52. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  53. if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  54. setbits_le32(&gpr->gpr[10], BIT(1));
  55. /*
  56. * set Region 0 attribute to allow secure and non-secure
  57. * read/write permission. Found some masters like usb dwc3
  58. * controllers can't work with secure memory.
  59. */
  60. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  61. }
  62. void set_wdog_reset(struct wdog_regs *wdog)
  63. {
  64. /*
  65. * Output WDOG_B signal to reset external pmic or POR_B decided by
  66. * the board design. Without external reset, the peripherals/DDR/
  67. * PMIC are not reset, that may cause system working abnormal.
  68. * WDZST bit is write-once only bit. Align this bit in kernel,
  69. * otherwise kernel code will have no chance to set this bit.
  70. */
  71. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  72. }
  73. static struct mm_region imx8m_mem_map[] = {
  74. {
  75. /* ROM */
  76. .virt = 0x0UL,
  77. .phys = 0x0UL,
  78. .size = 0x100000UL,
  79. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  80. PTE_BLOCK_OUTER_SHARE
  81. }, {
  82. /* CAAM */
  83. .virt = 0x100000UL,
  84. .phys = 0x100000UL,
  85. .size = 0x8000UL,
  86. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  87. PTE_BLOCK_NON_SHARE |
  88. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  89. }, {
  90. /* TCM */
  91. .virt = 0x7C0000UL,
  92. .phys = 0x7C0000UL,
  93. .size = 0x80000UL,
  94. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  95. PTE_BLOCK_NON_SHARE |
  96. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  97. }, {
  98. /* OCRAM */
  99. .virt = 0x900000UL,
  100. .phys = 0x900000UL,
  101. .size = 0x200000UL,
  102. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  103. PTE_BLOCK_OUTER_SHARE
  104. }, {
  105. /* AIPS */
  106. .virt = 0xB00000UL,
  107. .phys = 0xB00000UL,
  108. .size = 0x3f500000UL,
  109. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  110. PTE_BLOCK_NON_SHARE |
  111. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  112. }, {
  113. /* DRAM1 */
  114. .virt = 0x40000000UL,
  115. .phys = 0x40000000UL,
  116. .size = PHYS_SDRAM_SIZE,
  117. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  118. PTE_BLOCK_OUTER_SHARE
  119. #ifdef PHYS_SDRAM_2_SIZE
  120. }, {
  121. /* DRAM2 */
  122. .virt = 0x100000000UL,
  123. .phys = 0x100000000UL,
  124. .size = PHYS_SDRAM_2_SIZE,
  125. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  126. PTE_BLOCK_OUTER_SHARE
  127. #endif
  128. }, {
  129. /* List terminator */
  130. 0,
  131. }
  132. };
  133. struct mm_region *mem_map = imx8m_mem_map;
  134. void enable_caches(void)
  135. {
  136. /*
  137. * If OPTEE runs, remove OPTEE memory from MMU table to
  138. * avoid speculative prefetch. OPTEE runs at the top of
  139. * the first memory bank
  140. */
  141. if (rom_pointer[1])
  142. imx8m_mem_map[5].size -= rom_pointer[1];
  143. icache_enable();
  144. dcache_enable();
  145. }
  146. static u32 get_cpu_variant_type(u32 type)
  147. {
  148. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  149. struct fuse_bank *bank = &ocotp->bank[1];
  150. struct fuse_bank1_regs *fuse =
  151. (struct fuse_bank1_regs *)bank->fuse_regs;
  152. u32 value = readl(&fuse->tester4);
  153. if (type == MXC_CPU_IMX8MQ) {
  154. if ((value & 0x3) == 0x2)
  155. return MXC_CPU_IMX8MD;
  156. else if (value & 0x200000)
  157. return MXC_CPU_IMX8MQL;
  158. } else if (type == MXC_CPU_IMX8MM) {
  159. switch (value & 0x3) {
  160. case 2:
  161. if (value & 0x1c0000)
  162. return MXC_CPU_IMX8MMDL;
  163. else
  164. return MXC_CPU_IMX8MMD;
  165. case 3:
  166. if (value & 0x1c0000)
  167. return MXC_CPU_IMX8MMSL;
  168. else
  169. return MXC_CPU_IMX8MMS;
  170. default:
  171. if (value & 0x1c0000)
  172. return MXC_CPU_IMX8MML;
  173. break;
  174. }
  175. } else if (type == MXC_CPU_IMX8MN) {
  176. switch (value & 0x3) {
  177. case 2:
  178. if (value & 0x1000000)
  179. return MXC_CPU_IMX8MNDL;
  180. else
  181. return MXC_CPU_IMX8MND;
  182. case 3:
  183. if (value & 0x1000000)
  184. return MXC_CPU_IMX8MNSL;
  185. else
  186. return MXC_CPU_IMX8MNS;
  187. default:
  188. if (value & 0x1000000)
  189. return MXC_CPU_IMX8MNL;
  190. break;
  191. }
  192. }
  193. return type;
  194. }
  195. u32 get_cpu_rev(void)
  196. {
  197. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  198. u32 reg = readl(&ana_pll->digprog);
  199. u32 type = (reg >> 16) & 0xff;
  200. u32 major_low = (reg >> 8) & 0xff;
  201. u32 rom_version;
  202. reg &= 0xff;
  203. /* iMX8MP */
  204. if (major_low == 0x43) {
  205. return (MXC_CPU_IMX8MP << 12) | reg;
  206. } else if (major_low == 0x42) {
  207. /* iMX8MN */
  208. type = get_cpu_variant_type(MXC_CPU_IMX8MN);
  209. } else if (major_low == 0x41) {
  210. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  211. } else {
  212. if (reg == CHIP_REV_1_0) {
  213. /*
  214. * For B0 chip, the DIGPROG is not updated,
  215. * it is still TO1.0. we have to check ROM
  216. * version or OCOTP_READ_FUSE_DATA.
  217. * 0xff0055aa is magic number for B1.
  218. */
  219. if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
  220. reg = CHIP_REV_2_1;
  221. } else {
  222. rom_version =
  223. readl((void __iomem *)ROM_VERSION_A0);
  224. if (rom_version != CHIP_REV_1_0) {
  225. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  226. rom_version &= 0xff;
  227. if (rom_version == CHIP_REV_2_0)
  228. reg = CHIP_REV_2_0;
  229. }
  230. }
  231. }
  232. type = get_cpu_variant_type(type);
  233. }
  234. return (type << 12) | reg;
  235. }
  236. static void imx_set_wdog_powerdown(bool enable)
  237. {
  238. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  239. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  240. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  241. /* Write to the PDE (Power Down Enable) bit */
  242. writew(enable, &wdog1->wmcr);
  243. writew(enable, &wdog2->wmcr);
  244. writew(enable, &wdog3->wmcr);
  245. }
  246. int arch_cpu_init_dm(void)
  247. {
  248. struct udevice *dev;
  249. int ret;
  250. if (CONFIG_IS_ENABLED(CLK)) {
  251. ret = uclass_get_device_by_name(UCLASS_CLK,
  252. "clock-controller@30380000",
  253. &dev);
  254. if (ret < 0) {
  255. printf("Failed to find clock node. Check device tree\n");
  256. return ret;
  257. }
  258. }
  259. return 0;
  260. }
  261. int arch_cpu_init(void)
  262. {
  263. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  264. /*
  265. * ROM might disable clock for SCTR,
  266. * enable the clock before timer_init.
  267. */
  268. if (IS_ENABLED(CONFIG_SPL_BUILD))
  269. clock_enable(CCGR_SCTR, 1);
  270. /*
  271. * Init timer at very early state, because sscg pll setting
  272. * will use it
  273. */
  274. timer_init();
  275. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  276. clock_init();
  277. imx_set_wdog_powerdown(false);
  278. }
  279. if (is_imx8mq()) {
  280. clock_enable(CCGR_OCOTP, 1);
  281. if (readl(&ocotp->ctrl) & 0x200)
  282. writel(0x200, &ocotp->ctrl_clr);
  283. }
  284. return 0;
  285. }
  286. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  287. struct rom_api *g_rom_api = (struct rom_api *)0x980;
  288. enum boot_device get_boot_device(void)
  289. {
  290. volatile gd_t *pgd = gd;
  291. int ret;
  292. u32 boot;
  293. u16 boot_type;
  294. u8 boot_instance;
  295. enum boot_device boot_dev = SD1_BOOT;
  296. ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  297. ((uintptr_t)&boot) ^ QUERY_BT_DEV);
  298. gd = pgd;
  299. if (ret != ROM_API_OKAY) {
  300. puts("ROMAPI: failure at query_boot_info\n");
  301. return -1;
  302. }
  303. boot_type = boot >> 16;
  304. boot_instance = (boot >> 8) & 0xff;
  305. switch (boot_type) {
  306. case BT_DEV_TYPE_SD:
  307. boot_dev = boot_instance + SD1_BOOT;
  308. break;
  309. case BT_DEV_TYPE_MMC:
  310. boot_dev = boot_instance + MMC1_BOOT;
  311. break;
  312. case BT_DEV_TYPE_NAND:
  313. boot_dev = NAND_BOOT;
  314. break;
  315. case BT_DEV_TYPE_FLEXSPINOR:
  316. boot_dev = QSPI_BOOT;
  317. break;
  318. case BT_DEV_TYPE_USB:
  319. boot_dev = USB_BOOT;
  320. break;
  321. default:
  322. break;
  323. }
  324. return boot_dev;
  325. }
  326. #endif
  327. bool is_usb_boot(void)
  328. {
  329. return get_boot_device() == USB_BOOT;
  330. }
  331. #ifdef CONFIG_OF_SYSTEM_SETUP
  332. int ft_system_setup(void *blob, bd_t *bd)
  333. {
  334. int i = 0;
  335. int rc;
  336. int nodeoff;
  337. /* Disable the CPU idle for A0 chip since the HW does not support it */
  338. if (is_soc_rev(CHIP_REV_1_0)) {
  339. static const char * const nodes_path[] = {
  340. "/cpus/cpu@0",
  341. "/cpus/cpu@1",
  342. "/cpus/cpu@2",
  343. "/cpus/cpu@3",
  344. };
  345. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  346. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  347. if (nodeoff < 0)
  348. continue; /* Not found, skip it */
  349. debug("Found %s node\n", nodes_path[i]);
  350. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  351. if (rc == -FDT_ERR_NOTFOUND)
  352. continue;
  353. if (rc) {
  354. printf("Unable to update property %s:%s, err=%s\n",
  355. nodes_path[i], "status", fdt_strerror(rc));
  356. return rc;
  357. }
  358. debug("Remove %s:%s\n", nodes_path[i],
  359. "cpu-idle-states");
  360. }
  361. }
  362. return 0;
  363. }
  364. #endif
  365. #if !CONFIG_IS_ENABLED(SYSRESET)
  366. void reset_cpu(ulong addr)
  367. {
  368. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  369. /* Clear WDA to trigger WDOG_B immediately */
  370. writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
  371. while (1) {
  372. /*
  373. * spin for .5 seconds before reset
  374. */
  375. }
  376. }
  377. #endif
  378. #if defined(CONFIG_ARCH_MISC_INIT)
  379. static void acquire_buildinfo(void)
  380. {
  381. u64 atf_commit = 0;
  382. /* Get ARM Trusted Firmware commit id */
  383. atf_commit = call_imx_sip(IMX_SIP_BUILDINFO,
  384. IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0);
  385. if (atf_commit == 0xffffffff) {
  386. debug("ATF does not support build info\n");
  387. atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
  388. }
  389. printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
  390. }
  391. int arch_misc_init(void)
  392. {
  393. acquire_buildinfo();
  394. return 0;
  395. }
  396. #endif
  397. void imx_tmu_arch_init(void *reg_base)
  398. {
  399. if (is_imx8mm() || is_imx8mn()) {
  400. /* Load TCALIV and TASR from fuses */
  401. struct ocotp_regs *ocotp =
  402. (struct ocotp_regs *)OCOTP_BASE_ADDR;
  403. struct fuse_bank *bank = &ocotp->bank[3];
  404. struct fuse_bank3_regs *fuse =
  405. (struct fuse_bank3_regs *)bank->fuse_regs;
  406. u32 tca_rt, tca_hr, tca_en;
  407. u32 buf_vref, buf_slope;
  408. tca_rt = fuse->ana0 & 0xFF;
  409. tca_hr = (fuse->ana0 & 0xFF00) >> 8;
  410. tca_en = (fuse->ana0 & 0x2000000) >> 25;
  411. buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
  412. buf_slope = (fuse->ana0 & 0xF0000) >> 16;
  413. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  414. writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
  415. (ulong)reg_base + 0x30);
  416. }
  417. #ifdef CONFIG_IMX8MP
  418. /* Load TCALIV0/1/m40 and TRIM from fuses */
  419. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  420. struct fuse_bank *bank = &ocotp->bank[38];
  421. struct fuse_bank38_regs *fuse =
  422. (struct fuse_bank38_regs *)bank->fuse_regs;
  423. struct fuse_bank *bank2 = &ocotp->bank[39];
  424. struct fuse_bank39_regs *fuse2 =
  425. (struct fuse_bank39_regs *)bank2->fuse_regs;
  426. u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
  427. u32 reg;
  428. u32 tca40[2], tca25[2], tca105[2];
  429. /* For blank sample */
  430. if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
  431. !fuse->ana_trim4 && !fuse2->ana_trim5) {
  432. /* Use a default 25C binary codes */
  433. tca25[0] = 1596;
  434. tca25[1] = 1596;
  435. writel(tca25[0], (ulong)reg_base + 0x30);
  436. writel(tca25[1], (ulong)reg_base + 0x34);
  437. return;
  438. }
  439. buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
  440. buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
  441. bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
  442. bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
  443. vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
  444. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  445. reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
  446. writel(reg, (ulong)reg_base + 0x3c);
  447. tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
  448. tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
  449. tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
  450. tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
  451. tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
  452. tca25[1] = fuse2->ana_trim5 & 0xFFF;
  453. tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
  454. /* use 25c for 1p calibration */
  455. writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
  456. writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
  457. writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
  458. #endif
  459. }