at91_sfr.h 3.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Special Function Register (SFR)
  4. *
  5. * Copyright (C) 2014 Atmel
  6. * Bo Shen <voice.shen@atmel.com>
  7. */
  8. #ifndef __AT91_SFR_H
  9. #define __AT91_SFR_H
  10. #include <linux/bitops.h>
  11. struct atmel_sfr {
  12. u32 reserved1; /* 0x00 */
  13. union {
  14. u32 ddrcfg; /* 0x04: DDR Configuration Register */
  15. u32 ebicsa; /* 0x04: EBI Chip Select Register */
  16. };
  17. u32 reserved2; /* 0x08 */
  18. u32 reserved3; /* 0x0c */
  19. u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */
  20. u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */
  21. u32 reserved4[4]; /* 0x18 ~ 0x24 */
  22. u32 secure; /* 0x28: Security Configuration Register */
  23. u32 reserved5[5]; /* 0x2c ~ 0x3c */
  24. u32 ebicfg; /* 0x40: EBI Configuration Register */
  25. u32 reserved6[2]; /* 0x44 ~ 0x48 */
  26. u32 sn0; /* 0x4c */
  27. u32 sn1; /* 0x50 */
  28. u32 aicredir; /* 0x54 */
  29. u32 l2cc_hramc; /* 0x58 */
  30. };
  31. /* Register Mapping*/
  32. #define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */
  33. #define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */
  34. /* 0x08 ~ 0x0c: Reserved */
  35. #define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */
  36. #define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */
  37. #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */
  38. #define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */
  39. #define AT91_SFR_LS 0x7c /* Light Sleep Register */
  40. #define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */
  41. #define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */
  42. /* Bit field in DDRCFG */
  43. #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
  44. #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
  45. /* Bit field in EBICFG */
  46. #define AT91_SFR_EBICFG_DRIVE0 (0x3 << 0)
  47. #define AT91_SFR_EBICFG_DRIVE0_LOW (0x0 << 0)
  48. #define AT91_SFR_EBICFG_DRIVE0_MEDIUM (0x2 << 0)
  49. #define AT91_SFR_EBICFG_DRIVE0_HIGH (0x3 << 0)
  50. #define AT91_SFR_EBICFG_PULL0 (0x3 << 2)
  51. #define AT91_SFR_EBICFG_PULL0_UP (0x0 << 2)
  52. #define AT91_SFR_EBICFG_PULL0_NONE (0x1 << 2)
  53. #define AT91_SFR_EBICFG_PULL0_DOWN (0x3 << 2)
  54. #define AT91_SFR_EBICFG_SCH0 (0x1 << 4)
  55. #define AT91_SFR_EBICFG_SCH0_OFF (0x0 << 4)
  56. #define AT91_SFR_EBICFG_SCH0_ON (0x1 << 4)
  57. #define AT91_SFR_EBICFG_DRIVE1 (0x3 << 8)
  58. #define AT91_SFR_EBICFG_DRIVE1_LOW (0x0 << 8)
  59. #define AT91_SFR_EBICFG_DRIVE1_MEDIUM (0x2 << 8)
  60. #define AT91_SFR_EBICFG_DRIVE1_HIGH (0x3 << 8)
  61. #define AT91_SFR_EBICFG_PULL1 (0x3 << 10)
  62. #define AT91_SFR_EBICFG_PULL1_UP (0x0 << 10)
  63. #define AT91_SFR_EBICFG_PULL1_NONE (0x1 << 10)
  64. #define AT91_SFR_EBICFG_PULL1_DOWN (0x3 << 10)
  65. #define AT91_SFR_EBICFG_SCH1 (0x1 << 12)
  66. #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)
  67. #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12)
  68. /* Bit field in AICREDIR */
  69. #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
  70. /* Bit field in DDRCFG */
  71. #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
  72. #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
  73. #define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs))
  74. #define AT91_SFR_CCFG_EBI_DBPUC BIT(8)
  75. #define AT91_SFR_CCFG_EBI_DBPDC BIT(9)
  76. #define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60 BIT(16)
  77. #define AT91_SFR_CCFG_EBI_DRIVE BIT(17)
  78. #define AT91_SFR_CCFG_DQIEN_F BIT(20)
  79. #define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24)
  80. #define AT91_SFR_CCFG_DDR_MP_EN BIT(25)
  81. #define AT91_SFR_OHCIICR_RES(x) BIT(x)
  82. #define AT91_SFR_OHCIICR_ARIE BIT(4)
  83. #define AT91_SFR_OHCIICR_APPSTART BIT(5)
  84. #define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x))
  85. #define AT91_SFR_OHCIICR_UDPPUDIS BIT(23)
  86. #define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)
  87. #define AT91_SFR_OHCIISR_RIS(x) BIT(x)
  88. #define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
  89. #define AT91_SFR_UTMISWAP_PORT(x) BIT(x)
  90. #define AT91_SFR_LS_VALUE(x) BIT(x)
  91. #define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16)
  92. #define AT91_SFR_WPMR_WPEN BIT(0)
  93. #define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)
  94. #endif