keystone_net.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * emac definitions for keystone2 devices
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #ifndef _KEYSTONE_NET_H_
  9. #define _KEYSTONE_NET_H_
  10. #include <asm/io.h>
  11. #include <phy.h>
  12. #ifndef __ASSEMBLY__
  13. #include <linux/bitops.h>
  14. #endif
  15. /* EMAC */
  16. #ifdef CONFIG_KSNET_NETCP_V1_0
  17. #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000)
  18. #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900)
  19. #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300)
  20. #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100)
  21. #define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
  22. /* Register offsets */
  23. #define CPGMACSL_REG_CTL 0x04
  24. #define CPGMACSL_REG_STATUS 0x08
  25. #define CPGMACSL_REG_RESET 0x0c
  26. #define CPGMACSL_REG_MAXLEN 0x10
  27. #elif defined CONFIG_KSNET_NETCP_V1_5
  28. #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000)
  29. #define CPGMACSL_REG_RX_PRI_MAP 0x020
  30. #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000)
  31. #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00)
  32. #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100)
  33. #define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
  34. /* Register offsets */
  35. #define CPGMACSL_REG_CTL 0x330
  36. #define CPGMACSL_REG_STATUS 0x334
  37. #define CPGMACSL_REG_RESET 0x338
  38. #define CPGMACSL_REG_MAXLEN 0x024
  39. #endif
  40. #define KEYSTONE2_EMAC_GIG_ENABLE
  41. #define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE
  42. /* MDIO module input frequency */
  43. #ifdef CONFIG_SOC_K2G
  44. #define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk))
  45. #else
  46. #define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk))
  47. #endif
  48. /* MDIO clock output frequency */
  49. #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
  50. #define EMAC_MACCONTROL_MIIEN_ENABLE 0x20
  51. #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1
  52. #define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
  53. #define EMAC_MACCONTROL_GIGFORCE BIT(17)
  54. #define EMAC_MACCONTROL_RMIISPEED_100 BIT(15)
  55. #define EMAC_MIN_ETHERNET_PKT_SIZE 60
  56. struct mac_sl_cfg {
  57. u_int32_t max_rx_len; /* Maximum receive packet length. */
  58. u_int32_t ctl; /* Control bitfield */
  59. };
  60. /**
  61. * Definition: Control bitfields used in the ctl field of mac_sl_cfg
  62. */
  63. #define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24)
  64. #define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23)
  65. #define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22)
  66. #define GMACSL_RX_ENABLE_EXT_CTL BIT(18)
  67. #define GMACSL_RX_ENABLE_GIG_FORCE BIT(17)
  68. #define GMACSL_RX_ENABLE_IFCTL_B BIT(16)
  69. #define GMACSL_RX_ENABLE_IFCTL_A BIT(15)
  70. #define GMACSL_RX_ENABLE_CMD_IDLE BIT(11)
  71. #define GMACSL_TX_ENABLE_SHORT_GAP BIT(10)
  72. #define GMACSL_ENABLE_GIG_MODE BIT(7)
  73. #define GMACSL_TX_ENABLE_PACE BIT(6)
  74. #define GMACSL_ENABLE BIT(5)
  75. #define GMACSL_TX_ENABLE_FLOW_CTL BIT(4)
  76. #define GMACSL_RX_ENABLE_FLOW_CTL BIT(3)
  77. #define GMACSL_ENABLE_LOOPBACK BIT(1)
  78. #define GMACSL_ENABLE_FULL_DUPLEX BIT(0)
  79. /* EMAC SL function return values */
  80. #define GMACSL_RET_OK 0
  81. #define GMACSL_RET_INVALID_PORT -1
  82. #define GMACSL_RET_WARN_RESET_INCOMPLETE -2
  83. #define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
  84. #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
  85. /* EMAC SL register definitions */
  86. #define DEVICE_EMACSL_RESET_POLL_COUNT 100
  87. /* Soft reset register values */
  88. #define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0)
  89. #define CPGMAC_REG_RESET_VAL_RESET BIT(0)
  90. #define CPGMAC_REG_MAXLEN_LEN 0x3fff
  91. /* CPSW */
  92. /* Control bitfields */
  93. #define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5)
  94. #define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4)
  95. #define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3)
  96. #define CPSW_CTL_P0_ENABLE BIT(2)
  97. #define CPSW_CTL_VLAN_AWARE BIT(1)
  98. #define CPSW_CTL_FIFO_LOOPBACK BIT(0)
  99. #define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS
  100. #define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1)
  101. #ifdef CONFIG_KSNET_NETCP_V1_0
  102. #define DEVICE_CPSW_BASE (GBETH_BASE + 0x800)
  103. #define CPSW_REG_CTL 0x004
  104. #define CPSW_REG_STAT_PORT_EN 0x00c
  105. #define CPSW_REG_MAXLEN 0x040
  106. #define CPSW_REG_ALE_CONTROL 0x608
  107. #define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4)
  108. #define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
  109. #elif defined CONFIG_KSNET_NETCP_V1_5
  110. #define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000)
  111. #define CPSW_REG_CTL 0x00004
  112. #define CPSW_REG_STAT_PORT_EN 0x00014
  113. #define CPSW_REG_MAXLEN 0x01024
  114. #define CPSW_REG_ALE_CONTROL 0x1e008
  115. #define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4)
  116. #define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff
  117. #endif
  118. #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
  119. #define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
  120. #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
  121. #define target_get_switch_ctl() CPSW_CTL_P0_ENABLE
  122. #define SWITCH_MAX_PKT_SIZE 9000
  123. /* SGMII */
  124. #define SGMII_REG_STATUS_LOCK BIT(4)
  125. #define SGMII_REG_STATUS_LINK BIT(0)
  126. #define SGMII_REG_STATUS_AUTONEG BIT(2)
  127. #define SGMII_REG_CONTROL_AUTONEG BIT(0)
  128. #define SGMII_REG_CONTROL_MASTER BIT(5)
  129. #define SGMII_REG_MR_ADV_ENABLE BIT(0)
  130. #define SGMII_REG_MR_ADV_LINK BIT(15)
  131. #define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
  132. #define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
  133. #define SGMII_LINK_MAC_MAC_AUTONEG 0
  134. #define SGMII_LINK_MAC_PHY 1
  135. #define SGMII_LINK_MAC_MAC_FORCED 2
  136. #define SGMII_LINK_MAC_FIBER 3
  137. #define SGMII_LINK_MAC_PHY_FORCED 4
  138. #ifdef CONFIG_KSNET_NETCP_V1_0
  139. #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
  140. #elif defined CONFIG_KSNET_NETCP_V1_5
  141. #define SGMII_OFFSET(x) ((x) * 0x100)
  142. #endif
  143. #define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
  144. #define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
  145. #define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
  146. #define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
  147. #define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
  148. #define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
  149. #define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
  150. #define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
  151. #define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
  152. /* RGMII */
  153. #define RGMII_REG_STATUS_LINK BIT(0)
  154. #define RGMII_STATUS_REG (GBETH_BASE + 0x18)
  155. /* PSS */
  156. #ifdef CONFIG_KSNET_NETCP_V1_0
  157. #define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604)
  158. #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606
  159. #define hw_config_streaming_switch()\
  160. writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
  161. #elif defined CONFIG_KSNET_NETCP_V1_5
  162. #define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500)
  163. #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0
  164. #define hw_config_streaming_switch()\
  165. writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
  166. DEVICE_PSTREAM_CFG_REG_ADDR);\
  167. writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
  168. DEVICE_PSTREAM_CFG_REG_ADDR+4);\
  169. writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
  170. DEVICE_PSTREAM_CFG_REG_ADDR+8);\
  171. writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
  172. DEVICE_PSTREAM_CFG_REG_ADDR+12);
  173. #endif
  174. /* EMAC MDIO Registers Structure */
  175. struct mdio_regs {
  176. u32 version;
  177. u32 control;
  178. u32 alive;
  179. u32 link;
  180. u32 linkintraw;
  181. u32 linkintmasked;
  182. u32 rsvd0[2];
  183. u32 userintraw;
  184. u32 userintmasked;
  185. u32 userintmaskset;
  186. u32 userintmaskclear;
  187. u32 rsvd1[20];
  188. u32 useraccess0;
  189. u32 userphysel0;
  190. u32 useraccess1;
  191. u32 userphysel1;
  192. };
  193. #endif /* _KEYSTONE_NET_H_ */