omap_mmc.h 6.9 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Texas Instruments, <www.ti.com>
  4. * Syed Mohammed Khasim <khasim@ti.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation's version 2 of
  12. * the License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #ifndef OMAP_MMC_H_
  25. #define OMAP_MMC_H_
  26. #include <mmc.h>
  27. #ifndef __ASSEMBLY__
  28. #include <linux/bitops.h>
  29. #endif
  30. struct hsmmc {
  31. #ifndef CONFIG_OMAP34XX
  32. unsigned int hl_rev;
  33. unsigned int hl_hwinfo;
  34. unsigned int hl_sysconfig;
  35. unsigned char res0[0xf4];
  36. #endif
  37. unsigned char res1[0x10];
  38. unsigned int sysconfig; /* 0x10 */
  39. unsigned int sysstatus; /* 0x14 */
  40. unsigned char res2[0x14];
  41. unsigned int con; /* 0x2C */
  42. unsigned int pwcnt; /* 0x30 */
  43. unsigned int dll; /* 0x34 */
  44. unsigned char res3[0xcc];
  45. unsigned int blk; /* 0x104 */
  46. unsigned int arg; /* 0x108 */
  47. unsigned int cmd; /* 0x10C */
  48. unsigned int rsp10; /* 0x110 */
  49. unsigned int rsp32; /* 0x114 */
  50. unsigned int rsp54; /* 0x118 */
  51. unsigned int rsp76; /* 0x11C */
  52. unsigned int data; /* 0x120 */
  53. unsigned int pstate; /* 0x124 */
  54. unsigned int hctl; /* 0x128 */
  55. unsigned int sysctl; /* 0x12C */
  56. unsigned int stat; /* 0x130 */
  57. unsigned int ie; /* 0x134 */
  58. unsigned char res4[0x4];
  59. unsigned int ac12; /* 0x13C */
  60. unsigned int capa; /* 0x140 */
  61. unsigned int capa2; /* 0x144 */
  62. unsigned char res5[0xc];
  63. unsigned int admaes; /* 0x154 */
  64. unsigned int admasal; /* 0x158 */
  65. };
  66. struct omap_hsmmc_plat {
  67. struct mmc_config cfg;
  68. struct hsmmc *base_addr;
  69. struct mmc *mmc;
  70. u32 controller_flags;
  71. const char *hw_rev;
  72. };
  73. /*
  74. * OMAP HS MMC Bit definitions
  75. */
  76. #define MADMA_EN (0x1 << 0)
  77. #define MMC_SOFTRESET (0x1 << 1)
  78. #define RESETDONE (0x1 << 0)
  79. #define NOOPENDRAIN (0x0 << 0)
  80. #define OPENDRAIN (0x1 << 0)
  81. #define OD (0x1 << 0)
  82. #define INIT_NOINIT (0x0 << 1)
  83. #define INIT_INITSTREAM (0x1 << 1)
  84. #define HR_NOHOSTRESP (0x0 << 2)
  85. #define STR_BLOCK (0x0 << 3)
  86. #define MODE_FUNC (0x0 << 4)
  87. #define DW8_1_4BITMODE (0x0 << 5)
  88. #define MIT_CTO (0x0 << 6)
  89. #define CDP_ACTIVEHIGH (0x0 << 7)
  90. #define WPP_ACTIVEHIGH (0x0 << 8)
  91. #define RESERVED_MASK (0x3 << 9)
  92. #define CTPL_MMC_SD (0x0 << 11)
  93. #define DDR (0x1 << 19)
  94. #define DMA_MASTER (0x1 << 20)
  95. #define BLEN_512BYTESLEN (0x200 << 0)
  96. #define NBLK_STPCNT (0x0 << 16)
  97. #define DE_ENABLE (0x1 << 0)
  98. #define BCE_ENABLE (0x1 << 1)
  99. #define ACEN_ENABLE (0x1 << 2)
  100. #define DDIR_OFFSET (4)
  101. #define DDIR_MASK (0x1 << 4)
  102. #define DDIR_WRITE (0x0 << 4)
  103. #define DDIR_READ (0x1 << 4)
  104. #define MSBS_SGLEBLK (0x0 << 5)
  105. #define MSBS_MULTIBLK (0x1 << 5)
  106. #define RSP_TYPE_OFFSET (16)
  107. #define RSP_TYPE_MASK (0x3 << 16)
  108. #define RSP_TYPE_NORSP (0x0 << 16)
  109. #define RSP_TYPE_LGHT136 (0x1 << 16)
  110. #define RSP_TYPE_LGHT48 (0x2 << 16)
  111. #define RSP_TYPE_LGHT48B (0x3 << 16)
  112. #define CCCE_NOCHECK (0x0 << 19)
  113. #define CCCE_CHECK (0x1 << 19)
  114. #define CICE_NOCHECK (0x0 << 20)
  115. #define CICE_CHECK (0x1 << 20)
  116. #define DP_OFFSET (21)
  117. #define DP_MASK (0x1 << 21)
  118. #define DP_NO_DATA (0x0 << 21)
  119. #define DP_DATA (0x1 << 21)
  120. #define CMD_TYPE_NORMAL (0x0 << 22)
  121. #define INDEX_OFFSET (24)
  122. #define INDEX_MASK (0x3f << 24)
  123. #define INDEX(i) (i << 24)
  124. #define DATI_MASK (0x1 << 1)
  125. #define CMDI_MASK (0x1 << 0)
  126. #define DTW_1_BITMODE (0x0 << 1)
  127. #define DTW_4_BITMODE (0x1 << 1)
  128. #define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
  129. #define SDBP_PWROFF (0x0 << 8)
  130. #define SDBP_PWRON (0x1 << 8)
  131. #define SDVS_MASK (0x7 << 9)
  132. #define SDVS_1V8 (0x5 << 9)
  133. #define SDVS_3V0 (0x6 << 9)
  134. #define SDVS_3V3 (0x7 << 9)
  135. #define DMA_SELECT (0x2 << 3)
  136. #define ICE_MASK (0x1 << 0)
  137. #define ICE_STOP (0x0 << 0)
  138. #define ICS_MASK (0x1 << 1)
  139. #define ICS_NOTREADY (0x0 << 1)
  140. #define ICE_OSCILLATE (0x1 << 0)
  141. #define CEN_MASK (0x1 << 2)
  142. #define CEN_ENABLE (0x1 << 2)
  143. #define CLKD_OFFSET (6)
  144. #define CLKD_MASK (0x3FF << 6)
  145. #define DTO_MASK (0xF << 16)
  146. #define DTO_15THDTO (0xE << 16)
  147. #define SOFTRESETALL (0x1 << 24)
  148. #define CC_MASK (0x1 << 0)
  149. #define TC_MASK (0x1 << 1)
  150. #define BWR_MASK (0x1 << 4)
  151. #define BRR_MASK (0x1 << 5)
  152. #define ERRI_MASK (0x1 << 15)
  153. #define IE_CC (0x01 << 0)
  154. #define IE_TC (0x01 << 1)
  155. #define IE_BWR (0x01 << 4)
  156. #define IE_BRR (0x01 << 5)
  157. #define IE_CTO (0x01 << 16)
  158. #define IE_CCRC (0x01 << 17)
  159. #define IE_CEB (0x01 << 18)
  160. #define IE_CIE (0x01 << 19)
  161. #define IE_DTO (0x01 << 20)
  162. #define IE_DCRC (0x01 << 21)
  163. #define IE_DEB (0x01 << 22)
  164. #define IE_ADMAE (0x01 << 25)
  165. #define IE_CERR (0x01 << 28)
  166. #define IE_BADA (0x01 << 29)
  167. #define VS33_3V3SUP BIT(24)
  168. #define VS30_3V0SUP BIT(25)
  169. #define VS18_1V8SUP BIT(26)
  170. #define AC12_ET BIT(22)
  171. #define AC12_V1V8_SIGEN BIT(19)
  172. #define AC12_SCLK_SEL BIT(23)
  173. #define AC12_UHSMC_MASK (7 << 16)
  174. #define AC12_UHSMC_DDR50 (4 << 16)
  175. #define AC12_UHSMC_SDR104 (3 << 16)
  176. #define AC12_UHSMC_SDR50 (2 << 16)
  177. #define AC12_UHSMC_SDR25 (1 << 16)
  178. #define AC12_UHSMC_SDR12 (0 << 16)
  179. #define AC12_UHSMC_RES (0x7 << 16)
  180. /* Driver definitions */
  181. #define MMCSD_SECTOR_SIZE 512
  182. #define MMC_CARD 0
  183. #define SD_CARD 1
  184. #define BYTE_MODE 0
  185. #define SECTOR_MODE 1
  186. #define CLK_INITSEQ 0
  187. #define CLK_400KHZ 1
  188. #define CLK_MISC 2
  189. #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
  190. #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
  191. #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
  192. /* Clock Configurations and Macros */
  193. #ifdef CONFIG_OMAP54XX
  194. #define MMC_CLOCK_REFERENCE 192 /* MHz */
  195. #else
  196. #define MMC_CLOCK_REFERENCE 96 /* MHz */
  197. #endif
  198. /* DLL */
  199. #define DLL_SWT BIT(20)
  200. #define DLL_FORCE_SR_C_SHIFT 13
  201. #define DLL_FORCE_SR_C_MASK 0x7f
  202. #define DLL_FORCE_VALUE BIT(12)
  203. #define DLL_CALIB BIT(1)
  204. #define MAX_PHASE_DELAY 0x7c
  205. /* CAPA2 */
  206. #define CAPA2_TSDR50 BIT(13)
  207. #define mmc_reg_out(addr, mask, val)\
  208. writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
  209. #define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
  210. IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
  211. IE_BRR | IE_BWR | IE_TC | IE_CC)
  212. #define CON_CLKEXTFREE BIT(16)
  213. #define CON_PADEN BIT(15)
  214. #define PSTATE_CLEV BIT(24)
  215. #define PSTATE_DLEV (0xF << 20)
  216. #define PSTATE_DLEV_DAT0 (0x1 << 20)
  217. int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
  218. int wp_gpio);
  219. void vmmc_pbias_config(uint voltage);
  220. void board_mmc_poweron_ldo(uint voltage);
  221. #endif /* OMAP_MMC_H_ */