dc.h 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #ifndef __ASM_ARCH_TEGRA_DC_H
  7. #define __ASM_ARCH_TEGRA_DC_H
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. /* Register definitions for the Tegra display controller */
  12. /* CMD register 0x000 ~ 0x43 */
  13. struct dc_cmd_reg {
  14. /* Address 0x000 ~ 0x002 */
  15. uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */
  16. uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
  17. uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
  18. uint reserved0[5]; /* reserved_0[5] */
  19. /* Address 0x008 ~ 0x00a */
  20. uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */
  21. uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
  22. uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
  23. uint reserved1[5]; /* reserved_1[5] */
  24. /* Address 0x010 ~ 0x012 */
  25. uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */
  26. uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
  27. uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
  28. uint reserved2[5]; /* reserved_2[5] */
  29. /* Address 0x018 ~ 0x01a */
  30. uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */
  31. uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
  32. uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
  33. uint reserved3[13]; /* reserved_3[13] */
  34. /* Address 0x028 */
  35. uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */
  36. uint reserved4[7]; /* reserved_4[7] */
  37. /* Address 0x030 ~ 0x033 */
  38. uint ctxsw; /* _CMD_CTXSW_0 */
  39. uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */
  40. uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */
  41. uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */
  42. uint reserved5[2]; /* reserved_0[2] */
  43. /* Address 0x036 ~ 0x03e */
  44. uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */
  45. uint int_stat; /* _CMD_INT_STATUS_0 */
  46. uint int_mask; /* _CMD_INT_MASK_0 */
  47. uint int_enb; /* _CMD_INT_ENABLE_0 */
  48. uint int_type; /* _CMD_INT_TYPE_0 */
  49. uint int_polarity; /* _CMD_INT_POLARITY_0 */
  50. uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */
  51. uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */
  52. uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */
  53. uint reserved6; /* reserved_6 */
  54. /* Address 0x040 ~ 0x043 */
  55. uint state_access; /* _CMD_STATE_ACCESS_0 */
  56. uint state_ctrl; /* _CMD_STATE_CONTROL_0 */
  57. uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */
  58. uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */
  59. };
  60. enum {
  61. PIN_REG_COUNT = 4,
  62. PIN_OUTPUT_SEL_COUNT = 7,
  63. };
  64. /* COM register 0x300 ~ 0x329 */
  65. struct dc_com_reg {
  66. /* Address 0x300 ~ 0x301 */
  67. uint crc_ctrl; /* _COM_CRC_CONTROL_0 */
  68. uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */
  69. /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
  70. uint pin_output_enb[PIN_REG_COUNT];
  71. /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
  72. uint pin_output_polarity[PIN_REG_COUNT];
  73. /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
  74. uint pin_output_data[PIN_REG_COUNT];
  75. /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
  76. uint pin_input_enb[PIN_REG_COUNT];
  77. /* Address 0x312 ~ 0x313 */
  78. uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */
  79. uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */
  80. /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
  81. uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
  82. /* Address 0x31b ~ 0x329 */
  83. uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */
  84. uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */
  85. uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */
  86. uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */
  87. uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */
  88. uint spi_ctrl; /* _COM_SPI_CONTROL_0 */
  89. uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */
  90. uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */
  91. uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */
  92. uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */
  93. uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */
  94. uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */
  95. uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */
  96. uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
  97. uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */
  98. };
  99. enum dc_disp_h_pulse_pos {
  100. H_PULSE0_POSITION_A,
  101. H_PULSE0_POSITION_B,
  102. H_PULSE0_POSITION_C,
  103. H_PULSE0_POSITION_D,
  104. H_PULSE0_POSITION_COUNT,
  105. };
  106. struct _disp_h_pulse {
  107. /* _DISP_H_PULSE0/1/2_CONTROL_0 */
  108. uint h_pulse_ctrl;
  109. /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
  110. uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
  111. };
  112. enum dc_disp_v_pulse_pos {
  113. V_PULSE0_POSITION_A,
  114. V_PULSE0_POSITION_B,
  115. V_PULSE0_POSITION_C,
  116. V_PULSE0_POSITION_COUNT,
  117. };
  118. struct _disp_v_pulse0 {
  119. /* _DISP_H_PULSE0/1_CONTROL_0 */
  120. uint v_pulse_ctrl;
  121. /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
  122. uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
  123. };
  124. struct _disp_v_pulse2 {
  125. /* _DISP_H_PULSE2/3_CONTROL_0 */
  126. uint v_pulse_ctrl;
  127. /* _DISP_H_PULSE2/3_POSITION_A_0 */
  128. uint v_pulse_pos_a;
  129. };
  130. enum dc_disp_h_pulse_reg {
  131. H_PULSE0,
  132. H_PULSE1,
  133. H_PULSE2,
  134. H_PULSE_COUNT,
  135. };
  136. enum dc_disp_pp_select {
  137. PP_SELECT_A,
  138. PP_SELECT_B,
  139. PP_SELECT_C,
  140. PP_SELECT_D,
  141. PP_SELECT_COUNT,
  142. };
  143. /* DISP register 0x400 ~ 0x4c1 */
  144. struct dc_disp_reg {
  145. /* Address 0x400 ~ 0x40a */
  146. uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
  147. uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */
  148. uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */
  149. uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */
  150. uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
  151. uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */
  152. uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */
  153. uint sync_width; /* _DISP_SYNC_WIDTH_0 */
  154. uint back_porch; /* _DISP_BACK_PORCH_0 */
  155. uint disp_active; /* _DISP_DISP_ACTIVE_0 */
  156. uint front_porch; /* _DISP_FRONT_PORCH_0 */
  157. /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */
  158. struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
  159. /* Address 0x41a ~ 0x421 */
  160. struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
  161. struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
  162. /* Address 0x422 ~ 0x425 */
  163. struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
  164. struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
  165. /* Address 0x426 ~ 0x429 */
  166. uint m0_ctrl; /* _DISP_M0_CONTROL_0 */
  167. uint m1_ctrl; /* _DISP_M1_CONTROL_0 */
  168. uint di_ctrl; /* _DISP_DI_CONTROL_0 */
  169. uint pp_ctrl; /* _DISP_PP_CONTROL_0 */
  170. /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
  171. uint pp_select[PP_SELECT_COUNT];
  172. /* Address 0x42e ~ 0x435 */
  173. uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */
  174. uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */
  175. uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */
  176. uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */
  177. uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */
  178. uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
  179. uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */
  180. uint border_color; /* _DISP_BORDER_COLOR_0 */
  181. /* Address 0x436 ~ 0x439 */
  182. uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */
  183. uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */
  184. uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */
  185. uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */
  186. uint reserved0[2]; /* reserved_0[2] */
  187. /* Address 0x43c ~ 0x442 */
  188. uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */
  189. uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */
  190. uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */
  191. uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */
  192. uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */
  193. uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */
  194. uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */
  195. /* Address 0x443 ~ 0x446 */
  196. uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
  197. uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
  198. uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
  199. uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */
  200. uint reserved1[0x39]; /* reserved1[0x39], */
  201. /* Address 0x480 ~ 0x484 */
  202. uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */
  203. uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
  204. uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
  205. uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
  206. uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */
  207. uint reserved2[0x3b]; /* reserved2[0x3b] */
  208. /* Address 0x4c0 ~ 0x4c1 */
  209. uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */
  210. uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */
  211. u32 rsvd_4c2[34]; /* 4c2 - 4e3 */
  212. /* Address 0x4e4 */
  213. u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */
  214. };
  215. enum dc_winc_filter_p {
  216. WINC_FILTER_COUNT = 0x10,
  217. };
  218. /* Window A/B/C register 0x500 ~ 0x628 */
  219. struct dc_winc_reg {
  220. /* Address 0x500 */
  221. uint color_palette; /* _WINC_COLOR_PALETTE_0 */
  222. uint reserved0[0xff]; /* reserved_0[0xff] */
  223. /* Address 0x600 */
  224. uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */
  225. /* _WINC_H_FILTER_P00~0F_0 */
  226. /* Address 0x601 ~ 0x610 */
  227. uint h_filter_p[WINC_FILTER_COUNT];
  228. /* Address 0x611 ~ 0x618 */
  229. uint csc_yof; /* _WINC_CSC_YOF_0 */
  230. uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */
  231. uint csc_kur; /* _WINC_CSC_KUR_0 */
  232. uint csc_kvr; /* _WINC_CSC_KVR_0 */
  233. uint csc_kug; /* _WINC_CSC_KUG_0 */
  234. uint csc_kvg; /* _WINC_CSC_KVG_0 */
  235. uint csc_kub; /* _WINC_CSC_KUB_0 */
  236. uint csc_kvb; /* _WINC_CSC_KVB_0 */
  237. /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
  238. uint v_filter_p[WINC_FILTER_COUNT];
  239. };
  240. /* WIN A/B/C Register 0x700 ~ 0x719*/
  241. struct dc_win_reg {
  242. /* Address 0x700 ~ 0x719 */
  243. uint win_opt; /* _WIN_WIN_OPTIONS_0 */
  244. uint byte_swap; /* _WIN_BYTE_SWAP_0 */
  245. uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */
  246. uint color_depth; /* _WIN_COLOR_DEPTH_0 */
  247. uint pos; /* _WIN_POSITION_0 */
  248. uint size; /* _WIN_SIZE_0 */
  249. uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */
  250. uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */
  251. uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */
  252. uint dda_increment; /* _WIN_DDA_INCREMENT_0 */
  253. uint line_stride; /* _WIN_LINE_STRIDE_0 */
  254. uint buf_stride; /* _WIN_BUF_STRIDE_0 */
  255. uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */
  256. uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */
  257. uint dv_ctrl; /* _WIN_DV_CONTROL_0 */
  258. uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */
  259. uint blend_1win; /* _WIN_BLEND_1WIN_0 */
  260. uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */
  261. uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */
  262. uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */
  263. uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */
  264. uint global_alpha; /* _WIN_GLOBAL_ALPHA */
  265. uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */
  266. uint blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */
  267. uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */
  268. uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */
  269. };
  270. /* WINBUF A/B/C Register 0x800 ~ 0x80d */
  271. struct dc_winbuf_reg {
  272. /* Address 0x800 ~ 0x80d */
  273. uint start_addr; /* _WINBUF_START_ADDR_0 */
  274. uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */
  275. uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */
  276. uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */
  277. uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */
  278. uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */
  279. uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */
  280. uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */
  281. uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */
  282. uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */
  283. uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */
  284. uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */
  285. uint rsvd_80c;
  286. uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */
  287. };
  288. /* Display Controller (DC_) regs */
  289. struct dc_ctlr {
  290. struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */
  291. uint reserved0[0x2bc];
  292. struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */
  293. uint reserved1[0xd6];
  294. struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */
  295. uint reserved2[0x1b];
  296. struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */
  297. uint reserved3[0xd7];
  298. struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/
  299. uint reserved4[0xe6];
  300. struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */
  301. };
  302. /* DC_CMD_DISPLAY_COMMAND 0x032 */
  303. #define CTRL_MODE_SHIFT 5
  304. #define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
  305. enum {
  306. CTRL_MODE_STOP,
  307. CTRL_MODE_C_DISPLAY,
  308. CTRL_MODE_NC_DISPLAY,
  309. };
  310. /* _WIN_COLOR_DEPTH_0 */
  311. enum win_color_depth_id {
  312. COLOR_DEPTH_P1,
  313. COLOR_DEPTH_P2,
  314. COLOR_DEPTH_P4,
  315. COLOR_DEPTH_P8,
  316. COLOR_DEPTH_B4G4R4A4,
  317. COLOR_DEPTH_B5G5R5A,
  318. COLOR_DEPTH_B5G6R5,
  319. COLOR_DEPTH_AB5G5R5,
  320. COLOR_DEPTH_B8G8R8A8 = 12,
  321. COLOR_DEPTH_R8G8B8A8,
  322. COLOR_DEPTH_B6x2G6x2R6x2A8,
  323. COLOR_DEPTH_R6x2G6x2B6x2A8,
  324. COLOR_DEPTH_YCbCr422,
  325. COLOR_DEPTH_YUV422,
  326. COLOR_DEPTH_YCbCr420P,
  327. COLOR_DEPTH_YUV420P,
  328. COLOR_DEPTH_YCbCr422P,
  329. COLOR_DEPTH_YUV422P,
  330. COLOR_DEPTH_YCbCr422R,
  331. COLOR_DEPTH_YUV422R,
  332. COLOR_DEPTH_YCbCr422RA,
  333. COLOR_DEPTH_YUV422RA,
  334. };
  335. /* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
  336. #define PW0_ENABLE BIT(0)
  337. #define PW1_ENABLE BIT(2)
  338. #define PW2_ENABLE BIT(4)
  339. #define PW3_ENABLE BIT(6)
  340. #define PW4_ENABLE BIT(8)
  341. #define PM0_ENABLE BIT(16)
  342. #define PM1_ENABLE BIT(18)
  343. #define SPI_ENABLE BIT(24)
  344. #define HSPI_ENABLE BIT(25)
  345. /* DC_CMD_STATE_ACCESS 0x040 */
  346. #define READ_MUX_ASSEMBLY (0 << 0)
  347. #define READ_MUX_ACTIVE (1 << 0)
  348. #define WRITE_MUX_ASSEMBLY (0 << 2)
  349. #define WRITE_MUX_ACTIVE (1 << 2)
  350. /* DC_CMD_STATE_CONTROL 0x041 */
  351. #define GENERAL_ACT_REQ BIT(0)
  352. #define WIN_A_ACT_REQ BIT(1)
  353. #define WIN_B_ACT_REQ BIT(2)
  354. #define WIN_C_ACT_REQ BIT(3)
  355. #define WIN_D_ACT_REQ BIT(4)
  356. #define WIN_H_ACT_REQ BIT(5)
  357. #define CURSOR_ACT_REQ BIT(7)
  358. #define GENERAL_UPDATE BIT(8)
  359. #define WIN_A_UPDATE BIT(9)
  360. #define WIN_B_UPDATE BIT(10)
  361. #define WIN_C_UPDATE BIT(11)
  362. #define WIN_D_UPDATE BIT(12)
  363. #define WIN_H_UPDATE BIT(13)
  364. #define CURSOR_UPDATE BIT(15)
  365. #define NC_HOST_TRIG BIT(24)
  366. /* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
  367. #define WINDOW_A_SELECT BIT(4)
  368. #define WINDOW_B_SELECT BIT(5)
  369. #define WINDOW_C_SELECT BIT(6)
  370. #define WINDOW_D_SELECT BIT(7)
  371. #define WINDOW_H_SELECT BIT(8)
  372. /* DC_DISP_DISP_WIN_OPTIONS 0x402 */
  373. #define CURSOR_ENABLE BIT(16)
  374. #define SOR_ENABLE BIT(25)
  375. #define TVO_ENABLE BIT(28)
  376. #define DSI_ENABLE BIT(29)
  377. #define HDMI_ENABLE BIT(30)
  378. /* DC_DISP_DISP_TIMING_OPTIONS 0x405 */
  379. #define VSYNC_H_POSITION(x) ((x) & 0xfff)
  380. /* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
  381. #define SHIFT_CLK_DIVIDER_SHIFT 0
  382. #define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT)
  383. #define PIXEL_CLK_DIVIDER_SHIFT 8
  384. #define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT)
  385. enum {
  386. PIXEL_CLK_DIVIDER_PCD1,
  387. PIXEL_CLK_DIVIDER_PCD1H,
  388. PIXEL_CLK_DIVIDER_PCD2,
  389. PIXEL_CLK_DIVIDER_PCD3,
  390. PIXEL_CLK_DIVIDER_PCD4,
  391. PIXEL_CLK_DIVIDER_PCD6,
  392. PIXEL_CLK_DIVIDER_PCD8,
  393. PIXEL_CLK_DIVIDER_PCD9,
  394. PIXEL_CLK_DIVIDER_PCD12,
  395. PIXEL_CLK_DIVIDER_PCD16,
  396. PIXEL_CLK_DIVIDER_PCD18,
  397. PIXEL_CLK_DIVIDER_PCD24,
  398. PIXEL_CLK_DIVIDER_PCD13,
  399. };
  400. /* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
  401. #define DATA_FORMAT_SHIFT 0
  402. #define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT)
  403. enum {
  404. DATA_FORMAT_DF1P1C,
  405. DATA_FORMAT_DF1P2C24B,
  406. DATA_FORMAT_DF1P2C18B,
  407. DATA_FORMAT_DF1P2C16B,
  408. DATA_FORMAT_DF2S,
  409. DATA_FORMAT_DF3S,
  410. DATA_FORMAT_DFSPI,
  411. DATA_FORMAT_DF1P3C24B,
  412. DATA_FORMAT_DF1P3C18B,
  413. };
  414. #define DATA_ALIGNMENT_SHIFT 8
  415. enum {
  416. DATA_ALIGNMENT_MSB,
  417. DATA_ALIGNMENT_LSB,
  418. };
  419. #define DATA_ORDER_SHIFT 9
  420. enum {
  421. DATA_ORDER_RED_BLUE,
  422. DATA_ORDER_BLUE_RED,
  423. };
  424. /* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
  425. #define DE_SELECT_SHIFT 0
  426. #define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
  427. #define DE_SELECT_ACTIVE_BLANK 0x0
  428. #define DE_SELECT_ACTIVE 0x1
  429. #define DE_SELECT_ACTIVE_IS 0x2
  430. #define DE_CONTROL_SHIFT 2
  431. #define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT)
  432. enum {
  433. DE_CONTROL_ONECLK,
  434. DE_CONTROL_NORMAL,
  435. DE_CONTROL_EARLY_EXT,
  436. DE_CONTROL_EARLY,
  437. DE_CONTROL_ACTIVE_BLANK,
  438. };
  439. /* DC_WIN_WIN_OPTIONS 0x700 */
  440. #define H_DIRECTION BIT(0)
  441. enum {
  442. H_DIRECTION_INCREMENT,
  443. H_DIRECTION_DECREMENT,
  444. };
  445. #define V_DIRECTION BIT(2)
  446. enum {
  447. V_DIRECTION_INCREMENT,
  448. V_DIRECTION_DECREMENT,
  449. };
  450. #define COLOR_EXPAND BIT(6)
  451. #define CP_ENABLE BIT(16)
  452. #define DV_ENABLE BIT(20)
  453. #define WIN_ENABLE BIT(30)
  454. /* DC_WIN_BYTE_SWAP 0x701 */
  455. #define BYTE_SWAP_SHIFT 0
  456. #define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT)
  457. enum {
  458. BYTE_SWAP_NOSWAP,
  459. BYTE_SWAP_SWAP2,
  460. BYTE_SWAP_SWAP4,
  461. BYTE_SWAP_SWAP4HW
  462. };
  463. /* DC_WIN_POSITION 0x704 */
  464. #define H_POSITION_SHIFT 0
  465. #define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT)
  466. #define V_POSITION_SHIFT 16
  467. #define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT)
  468. /* DC_WIN_SIZE 0x705 */
  469. #define H_SIZE_SHIFT 0
  470. #define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT)
  471. #define V_SIZE_SHIFT 16
  472. #define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT)
  473. /* DC_WIN_PRESCALED_SIZE 0x706 */
  474. #define H_PRESCALED_SIZE_SHIFT 0
  475. #define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE)
  476. #define V_PRESCALED_SIZE_SHIFT 16
  477. #define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE)
  478. /* DC_WIN_DDA_INCREMENT 0x709 */
  479. #define H_DDA_INC_SHIFT 0
  480. #define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT)
  481. #define V_DDA_INC_SHIFT 16
  482. #define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
  483. #define DC_POLL_TIMEOUT_MS 50
  484. #define DC_N_WINDOWS 5
  485. #define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
  486. #endif /* __ASM_ARCH_TEGRA_DC_H */