dram_sun8i_a83t.h 6.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Sun8i platform dram controller register and constant defines
  4. *
  5. * (C) Copyright 2007-2015 Allwinner Technology Co.
  6. * Jerry Wang <wangflord@allwinnertech.com>
  7. * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
  8. * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
  9. */
  10. #ifndef _SUNXI_DRAM_SUN8I_A83T_H
  11. #define _SUNXI_DRAM_SUN8I_A83T_H
  12. #ifndef __ASSEMBLY__
  13. #include <linux/bitops.h>
  14. #endif
  15. struct sunxi_mctl_com_reg {
  16. u32 cr; /* 0x00 */
  17. u32 ccr; /* 0x04 controller configuration register */
  18. u32 dbgcr; /* 0x08 */
  19. u8 res0[0x4]; /* 0x0c */
  20. u32 mcr0_0; /* 0x10 */
  21. u32 mcr1_0; /* 0x14 */
  22. u32 mcr0_1; /* 0x18 */
  23. u32 mcr1_1; /* 0x1c */
  24. u32 mcr0_2; /* 0x20 */
  25. u32 mcr1_2; /* 0x24 */
  26. u32 mcr0_3; /* 0x28 */
  27. u32 mcr1_3; /* 0x2c */
  28. u32 mcr0_4; /* 0x30 */
  29. u32 mcr1_4; /* 0x34 */
  30. u32 mcr0_5; /* 0x38 */
  31. u32 mcr1_5; /* 0x3c */
  32. u32 mcr0_6; /* 0x40 */
  33. u32 mcr1_6; /* 0x44 */
  34. u32 mcr0_7; /* 0x48 */
  35. u32 mcr1_7; /* 0x4c */
  36. u32 mcr0_8; /* 0x50 */
  37. u32 mcr1_8; /* 0x54 */
  38. u32 mcr0_9; /* 0x58 */
  39. u32 mcr1_9; /* 0x5c */
  40. u32 mcr0_10; /* 0x60 */
  41. u32 mcr1_10; /* 0x64 */
  42. u32 mcr0_11; /* 0x68 */
  43. u32 mcr1_11; /* 0x6c */
  44. u32 mcr0_12; /* 0x70 */
  45. u32 mcr1_12; /* 0x74 */
  46. u32 mcr0_13; /* 0x78 */
  47. u32 mcr1_13; /* 0x7c */
  48. u32 mcr0_14; /* 0x80 */
  49. u32 mcr1_14; /* 0x84 */
  50. u32 mcr0_15; /* 0x88 */
  51. u32 mcr1_15; /* 0x8c */
  52. u32 bwcr; /* 0x90 */
  53. u32 maer; /* 0x94 */
  54. u32 mapr; /* 0x98 */
  55. u32 mcgcr; /* 0x9c */
  56. u32 bwctr; /* 0xa0 */
  57. u8 res2[0x8]; /* 0xa4 */
  58. u32 swoffr; /* 0xac */
  59. u8 res3[0x10]; /* 0xb0 */
  60. u32 swonr; /* 0xc0 */
  61. u8 res4[0x3c]; /* 0xc4 */
  62. u32 mdfscr; /* 0x100 */
  63. u32 mdfsmer; /* 0x104 */
  64. };
  65. struct sunxi_mctl_ctl_reg {
  66. u32 pir; /* 0x00 */
  67. u32 pwrctl; /* 0x04 */
  68. u32 mrctrl0; /* 0x08 */
  69. u32 clken; /* 0x0c */
  70. u32 pgsr0; /* 0x10 */
  71. u32 pgsr1; /* 0x14 */
  72. u32 statr; /* 0x18 */
  73. u8 res1[0x14]; /* 0x1c */
  74. u32 mr0; /* 0x30 */
  75. u32 mr1; /* 0x34 */
  76. u32 mr2; /* 0x38 */
  77. u32 mr3; /* 0x3c */
  78. u32 pllgcr; /* 0x40 */
  79. u32 ptr0; /* 0x44 */
  80. u32 ptr1; /* 0x48 */
  81. u32 ptr2; /* 0x4c */
  82. u32 ptr3; /* 0x50 */
  83. u32 ptr4; /* 0x54 */
  84. u32 dramtmg0; /* 0x58 dram timing parameters register 0 */
  85. u32 dramtmg1; /* 0x5c dram timing parameters register 1 */
  86. u32 dramtmg2; /* 0x60 dram timing parameters register 2 */
  87. u32 dramtmg3; /* 0x64 dram timing parameters register 3 */
  88. u32 dramtmg4; /* 0x68 dram timing parameters register 4 */
  89. u32 dramtmg5; /* 0x6c dram timing parameters register 5 */
  90. u32 dramtmg6; /* 0x70 dram timing parameters register 6 */
  91. u32 dramtmg7; /* 0x74 dram timing parameters register 7 */
  92. u32 dramtmg8; /* 0x78 dram timing parameters register 8 */
  93. u32 odtcfg; /* 0x7c */
  94. u32 pitmg0; /* 0x80 */
  95. u32 pitmg1; /* 0x84 */
  96. u8 res2[0x4]; /* 0x88 */
  97. u32 rfshctl0; /* 0x8c */
  98. u32 rfshtmg; /* 0x90 */
  99. u32 rfshctl1; /* 0x94 */
  100. u32 pwrtmg; /* 0x98 */
  101. u8 res3[0x20]; /* 0x9c */
  102. u32 dqsgmr; /* 0xbc */
  103. u32 dtcr; /* 0xc0 */
  104. u32 dtar0; /* 0xc4 */
  105. u32 dtar1; /* 0xc8 */
  106. u32 dtar2; /* 0xcc */
  107. u32 dtar3; /* 0xd0 */
  108. u32 dtdr0; /* 0xd4 */
  109. u32 dtdr1; /* 0xd8 */
  110. u32 dtmr0; /* 0xdc */
  111. u32 dtmr1; /* 0xe0 */
  112. u32 dtbmr; /* 0xe4 */
  113. u32 catr0; /* 0xe8 */
  114. u32 catr1; /* 0xec */
  115. u32 dtedr0; /* 0xf0 */
  116. u32 dtedr1; /* 0xf4 */
  117. u8 res4[0x8]; /* 0xf8 */
  118. u32 pgcr0; /* 0x100 */
  119. u32 pgcr1; /* 0x104 */
  120. u32 pgcr2; /* 0x108 */
  121. u32 pgcr3; /* 0x10c */
  122. u32 iovcr0; /* 0x110 */
  123. u32 iovcr1; /* 0x114 */
  124. u32 dqsdr; /* 0x118 */
  125. u32 dxccr; /* 0x11c */
  126. u32 odtmap; /* 0x120 */
  127. u32 zqctl0; /* 0x124 */
  128. u32 zqctl1; /* 0x128 */
  129. u8 res6[0x14]; /* 0x12c */
  130. u32 zqncr; /* 0x140 zq control register 0 */
  131. u32 zqnpr; /* 0x144 zq control register 1 */
  132. u32 zqndr; /* 0x148 zq control register 2 */
  133. u32 zqnsr; /* 0x14c zq status register 0 */
  134. u32 res7; /* 0x150 zq status register 1 */
  135. u8 res8[0x6c]; /* 0x154 */
  136. u32 sched; /* 0x1c0 */
  137. u32 perfhpr0; /* 0x1c4 */
  138. u32 perfhpr1; /* 0x1c8 */
  139. u32 perflpr0; /* 0x1cc */
  140. u32 perflpr1; /* 0x1d0 */
  141. u32 perfwr0; /* 0x1d4 */
  142. u32 perfwr1; /* 0x1d8 */
  143. };
  144. #define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
  145. #define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
  146. #define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)
  147. #define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
  148. #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
  149. #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
  150. #define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
  151. #define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
  152. #define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x))
  153. #define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x)
  154. #define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300)
  155. #define DXnLCDLR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x)
  156. #define DXnLCDLR1(x) (SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x)
  157. #define DXnLCDLR2(x) (SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x)
  158. #define DATX0IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x)
  159. #define DATX1IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x)
  160. #define DATX2IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x)
  161. #define DATX3IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x)
  162. #define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880)
  163. #define MX_UPD2 (SUNXI_DRAM_CTL0_BASE + 0x00000888)
  164. #define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800)
  165. #define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x)
  166. #define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x)
  167. /*
  168. * DRAM common (sunxi_mctl_com_reg) register constants.
  169. */
  170. #define MCTL_CR_RANK_MASK (3 << 0)
  171. #define MCTL_CR_RANK(x) (((x) - 1) << 0)
  172. #define MCTL_CR_BANK_MASK (3 << 2)
  173. #define MCTL_CR_BANK(x) ((x) << 2)
  174. #define MCTL_CR_ROW_MASK (0xf << 4)
  175. #define MCTL_CR_ROW(x) (((x) - 1) << 4)
  176. #define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
  177. #define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
  178. #define MCTL_CR_BUSW_MASK (7 << 12)
  179. #define MCTL_CR_BUSW8 (0 << 12)
  180. #define MCTL_CR_BUSW16 (1 << 12)
  181. #define MCTL_CR_SEQUENCE (1 << 15)
  182. #define MCTL_CR_DRAM_TYPE(x) ((x) << 16)
  183. #define MCTL_CR_CHANNEL_MASK (1 << 19)
  184. #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19)
  185. #define MCTL_CR_UNKNOWN (0x4 << 20)
  186. #define MCTL_CR_CS1_CONTROL(x) ((x) << 24)
  187. /* DRAM control (sunxi_mctl_ctl_reg) register constants */
  188. #define MCTL_MR0 0x1c70 /* CL=11, WR=12 */
  189. #define MCTL_MR1 0x40
  190. #define MCTL_MR2 0x18 /* CWL=8 */
  191. #define MCTL_MR3 0x0
  192. #define MCTL_LPDDR3_MR0 0x0
  193. #define MCTL_LPDDR3_MR1 0xc3 /* twr=8, bl=8 */
  194. #define MCTL_LPDDR3_MR2 0xa /* RL=12, CWL=6 */
  195. #define MCTL_LPDDR3_MR3 0x0
  196. #define DRAM_TYPE_DDR3 3
  197. #define DRAM_TYPE_LPDDR3 7
  198. #endif /* _SUNXI_DRAM_SUN8I_A83T_H */