sdhci.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  5. */
  6. #ifndef __STI_SDHCI_H__
  7. #define __STI_SDHCI_H__
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. #define FLASHSS_MMC_CORE_CONFIG_1 0x400
  12. #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24)
  13. #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12)
  14. #define STI_FLASHSS_MMC_CORE_CONFIG_1 \
  15. (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \
  16. FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
  17. #define FLASHSS_MMC_CORE_CONFIG_2 0x404
  18. #define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28)
  19. #define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20)
  20. #define MAX_BLK_LENGTH_1024 BIT(16)
  21. #define BASE_CLK_FREQ_200 0xc8
  22. #define STI_FLASHSS_MMC_CORE_CONFIG2 \
  23. (FLASHSS_MMC_CORECFG_HIGH_SPEED | \
  24. FLASHSS_MMC_CORECFG_8BIT_EMMC | \
  25. MAX_BLK_LENGTH_1024 | \
  26. BASE_CLK_FREQ_200 << 0)
  27. #define STI_FLASHSS_SDCARD_CORE_CONFIG2 \
  28. (FLASHSS_MMC_CORECFG_HIGH_SPEED | \
  29. MAX_BLK_LENGTH_1024 | \
  30. BASE_CLK_FREQ_200)
  31. #define FLASHSS_MMC_CORE_CONFIG_3 0x408
  32. #define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28)
  33. #define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20)
  34. #define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8)
  35. #define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4)
  36. #define FLASHSS_MMC_CORECFG_SDMA BIT(0)
  37. #define STI_FLASHSS_MMC_CORE_CONFIG3 \
  38. (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \
  39. FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
  40. FLASHSS_MMC_CORECFG_3P3_VOLT | \
  41. FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
  42. FLASHSS_MMC_CORECFG_SDMA)
  43. #define STI_FLASHSS_SDCARD_CORE_CONFIG3 \
  44. (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
  45. FLASHSS_MMC_CORECFG_3P3_VOLT | \
  46. FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
  47. FLASHSS_MMC_CORECFG_SDMA)
  48. #define FLASHSS_MMC_CORE_CONFIG_4 0x40c
  49. #define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20)
  50. #define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16)
  51. #define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12)
  52. #define STI_FLASHSS_MMC_CORE_CONFIG4 \
  53. (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \
  54. FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \
  55. FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
  56. #define ST_MMC_CCONFIG_REG_5 0x210
  57. #define SYSCONF_MMC1_ENABLE_BIT 3
  58. #endif /* _STI_SDHCI_H_ */