sdram_rk3399.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
  4. */
  5. #ifndef _ASM_ARCH_SDRAM_RK3399_H
  6. #define _ASM_ARCH_SDRAM_RK3399_H
  7. #include <asm/arch-rockchip/sdram_common.h>
  8. #include <asm/arch-rockchip/sdram_msch.h>
  9. #ifndef __ASSEMBLY__
  10. #include <linux/bitops.h>
  11. #endif
  12. struct rk3399_ddr_pctl_regs {
  13. u32 denali_ctl[332];
  14. };
  15. struct rk3399_ddr_publ_regs {
  16. u32 denali_phy[959];
  17. };
  18. struct rk3399_ddr_pi_regs {
  19. u32 denali_pi[200];
  20. };
  21. struct rk3399_ddr_cic_regs {
  22. u32 cic_ctrl0;
  23. u32 cic_ctrl1;
  24. u32 cic_idle_th;
  25. u32 cic_cg_wait_th;
  26. u32 cic_status0;
  27. u32 cic_status1;
  28. u32 cic_ctrl2;
  29. u32 cic_ctrl3;
  30. u32 cic_ctrl4;
  31. };
  32. /* DENALI_CTL_00 */
  33. #define START 1
  34. /* DENALI_CTL_68 */
  35. #define PWRUP_SREFRESH_EXIT BIT(16)
  36. /* DENALI_CTL_274 */
  37. #define MEM_RST_VALID 1
  38. struct msch_regs {
  39. u32 coreid;
  40. u32 revisionid;
  41. u32 ddrconf;
  42. u32 ddrsize;
  43. union noc_ddrtiminga0 ddrtiminga0;
  44. union noc_ddrtimingb0 ddrtimingb0;
  45. union noc_ddrtimingc0 ddrtimingc0;
  46. union noc_devtodev0 devtodev0;
  47. u32 reserved0[(0x110 - 0x20) / 4];
  48. union noc_ddrmode ddrmode;
  49. u32 reserved1[(0x1000 - 0x114) / 4];
  50. u32 agingx0;
  51. };
  52. struct sdram_msch_timings {
  53. union noc_ddrtiminga0 ddrtiminga0;
  54. union noc_ddrtimingb0 ddrtimingb0;
  55. union noc_ddrtimingc0 ddrtimingc0;
  56. union noc_devtodev0 devtodev0;
  57. union noc_ddrmode ddrmode;
  58. u32 agingx0;
  59. };
  60. struct rk3399_sdram_channel {
  61. struct sdram_cap_info cap_info;
  62. struct sdram_msch_timings noc_timings;
  63. };
  64. struct rk3399_sdram_params {
  65. struct rk3399_sdram_channel ch[2];
  66. struct sdram_base_params base;
  67. struct rk3399_ddr_pctl_regs pctl_regs;
  68. struct rk3399_ddr_pi_regs pi_regs;
  69. struct rk3399_ddr_publ_regs phy_regs;
  70. };
  71. #define PI_CA_TRAINING BIT(0)
  72. #define PI_WRITE_LEVELING BIT(1)
  73. #define PI_READ_GATE_TRAINING BIT(2)
  74. #define PI_READ_LEVELING BIT(3)
  75. #define PI_WDQ_LEVELING BIT(4)
  76. #define PI_FULL_TRAINING 0xff
  77. enum {
  78. STRIDE_128B = 0,
  79. STRIDE_256B = 1,
  80. STRIDE_512B = 2,
  81. STRIDE_4KB = 3,
  82. UN_STRIDE = 4,
  83. PART_STRIDE = 5,
  84. };
  85. #endif