sdram_rk322x.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #ifndef _ASM_ARCH_SDRAM_RK322X_H
  6. #define _ASM_ARCH_SDRAM_RK322X_H
  7. #ifndef __ASSEMBLY__
  8. #include <linux/bitops.h>
  9. #endif
  10. struct rk322x_sdram_channel {
  11. /*
  12. * bit width in address, eg:
  13. * 8 banks using 3 bit to address,
  14. * 2 cs using 1 bit to address.
  15. */
  16. u8 rank;
  17. u8 col;
  18. u8 bk;
  19. u8 bw;
  20. u8 dbw;
  21. u8 row_3_4;
  22. u8 cs0_row;
  23. u8 cs1_row;
  24. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  25. /*
  26. * For of-platdata, which would otherwise convert this into two
  27. * byte-swapped integers. With a size of 9 bytes, this struct will
  28. * appear in of-platdata as a byte array.
  29. *
  30. * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
  31. */
  32. u8 dummy;
  33. #endif
  34. };
  35. struct rk322x_ddr_pctl {
  36. u32 scfg;
  37. u32 sctl;
  38. u32 stat;
  39. u32 intrstat;
  40. u32 reserved0[(0x40 - 0x10) / 4];
  41. u32 mcmd;
  42. u32 powctl;
  43. u32 powstat;
  44. u32 cmdtstat;
  45. u32 cmdtstaten;
  46. u32 reserved1[(0x60 - 0x54) / 4];
  47. u32 mrrcfg0;
  48. u32 mrrstat0;
  49. u32 mrrstat1;
  50. u32 reserved2[(0x7c - 0x6c) / 4];
  51. u32 mcfg1;
  52. u32 mcfg;
  53. u32 ppcfg;
  54. u32 mstat;
  55. u32 lpddr2zqcfg;
  56. u32 reserved3;
  57. u32 dtupdes;
  58. u32 dtuna;
  59. u32 dtune;
  60. u32 dtuprd0;
  61. u32 dtuprd1;
  62. u32 dtuprd2;
  63. u32 dtuprd3;
  64. u32 dtuawdt;
  65. u32 reserved4[(0xc0 - 0xb4) / 4];
  66. u32 togcnt1u;
  67. u32 tinit;
  68. u32 trsth;
  69. u32 togcnt100n;
  70. u32 trefi;
  71. u32 tmrd;
  72. u32 trfc;
  73. u32 trp;
  74. u32 trtw;
  75. u32 tal;
  76. u32 tcl;
  77. u32 tcwl;
  78. u32 tras;
  79. u32 trc;
  80. u32 trcd;
  81. u32 trrd;
  82. u32 trtp;
  83. u32 twr;
  84. u32 twtr;
  85. u32 texsr;
  86. u32 txp;
  87. u32 txpdll;
  88. u32 tzqcs;
  89. u32 tzqcsi;
  90. u32 tdqs;
  91. u32 tcksre;
  92. u32 tcksrx;
  93. u32 tcke;
  94. u32 tmod;
  95. u32 trstl;
  96. u32 tzqcl;
  97. u32 tmrr;
  98. u32 tckesr;
  99. u32 tdpd;
  100. u32 tref_mem_ddr3;
  101. u32 reserved5[(0x180 - 0x14c) / 4];
  102. u32 ecccfg;
  103. u32 ecctst;
  104. u32 eccclr;
  105. u32 ecclog;
  106. u32 reserved6[(0x200 - 0x190) / 4];
  107. u32 dtuwactl;
  108. u32 dturactl;
  109. u32 dtucfg;
  110. u32 dtuectl;
  111. u32 dtuwd0;
  112. u32 dtuwd1;
  113. u32 dtuwd2;
  114. u32 dtuwd3;
  115. u32 dtuwdm;
  116. u32 dturd0;
  117. u32 dturd1;
  118. u32 dturd2;
  119. u32 dturd3;
  120. u32 dtulfsrwd;
  121. u32 dtulfsrrd;
  122. u32 dtueaf;
  123. /* dfi control registers */
  124. u32 dfitctrldelay;
  125. u32 dfiodtcfg;
  126. u32 dfiodtcfg1;
  127. u32 dfiodtrankmap;
  128. /* dfi write data registers */
  129. u32 dfitphywrdata;
  130. u32 dfitphywrlat;
  131. u32 reserved7[(0x260 - 0x258) / 4];
  132. u32 dfitrddataen;
  133. u32 dfitphyrdlat;
  134. u32 reserved8[(0x270 - 0x268) / 4];
  135. u32 dfitphyupdtype0;
  136. u32 dfitphyupdtype1;
  137. u32 dfitphyupdtype2;
  138. u32 dfitphyupdtype3;
  139. u32 dfitctrlupdmin;
  140. u32 dfitctrlupdmax;
  141. u32 dfitctrlupddly;
  142. u32 reserved9;
  143. u32 dfiupdcfg;
  144. u32 dfitrefmski;
  145. u32 dfitctrlupdi;
  146. u32 reserved10[(0x2ac - 0x29c) / 4];
  147. u32 dfitrcfg0;
  148. u32 dfitrstat0;
  149. u32 dfitrwrlvlen;
  150. u32 dfitrrdlvlen;
  151. u32 dfitrrdlvlgateen;
  152. u32 dfiststat0;
  153. u32 dfistcfg0;
  154. u32 dfistcfg1;
  155. u32 reserved11;
  156. u32 dfitdramclken;
  157. u32 dfitdramclkdis;
  158. u32 dfistcfg2;
  159. u32 dfistparclr;
  160. u32 dfistparlog;
  161. u32 reserved12[(0x2f0 - 0x2e4) / 4];
  162. u32 dfilpcfg0;
  163. u32 reserved13[(0x300 - 0x2f4) / 4];
  164. u32 dfitrwrlvlresp0;
  165. u32 dfitrwrlvlresp1;
  166. u32 dfitrwrlvlresp2;
  167. u32 dfitrrdlvlresp0;
  168. u32 dfitrrdlvlresp1;
  169. u32 dfitrrdlvlresp2;
  170. u32 dfitrwrlvldelay0;
  171. u32 dfitrwrlvldelay1;
  172. u32 dfitrwrlvldelay2;
  173. u32 dfitrrdlvldelay0;
  174. u32 dfitrrdlvldelay1;
  175. u32 dfitrrdlvldelay2;
  176. u32 dfitrrdlvlgatedelay0;
  177. u32 dfitrrdlvlgatedelay1;
  178. u32 dfitrrdlvlgatedelay2;
  179. u32 dfitrcmd;
  180. u32 reserved14[(0x3f8 - 0x340) / 4];
  181. u32 ipvr;
  182. u32 iptr;
  183. };
  184. check_member(rk322x_ddr_pctl, iptr, 0x03fc);
  185. struct rk322x_ddr_phy {
  186. u32 ddrphy_reg[0x100];
  187. };
  188. struct rk322x_pctl_timing {
  189. u32 togcnt1u;
  190. u32 tinit;
  191. u32 trsth;
  192. u32 togcnt100n;
  193. u32 trefi;
  194. u32 tmrd;
  195. u32 trfc;
  196. u32 trp;
  197. u32 trtw;
  198. u32 tal;
  199. u32 tcl;
  200. u32 tcwl;
  201. u32 tras;
  202. u32 trc;
  203. u32 trcd;
  204. u32 trrd;
  205. u32 trtp;
  206. u32 twr;
  207. u32 twtr;
  208. u32 texsr;
  209. u32 txp;
  210. u32 txpdll;
  211. u32 tzqcs;
  212. u32 tzqcsi;
  213. u32 tdqs;
  214. u32 tcksre;
  215. u32 tcksrx;
  216. u32 tcke;
  217. u32 tmod;
  218. u32 trstl;
  219. u32 tzqcl;
  220. u32 tmrr;
  221. u32 tckesr;
  222. u32 tdpd;
  223. u32 trefi_mem_ddr3;
  224. };
  225. struct rk322x_phy_timing {
  226. u32 mr[4];
  227. u32 mr11;
  228. u32 bl;
  229. u32 cl_al;
  230. };
  231. struct rk322x_msch_timings {
  232. u32 ddrtiming;
  233. u32 ddrmode;
  234. u32 readlatency;
  235. u32 activate;
  236. u32 devtodev;
  237. };
  238. struct rk322x_service_sys {
  239. u32 id_coreid;
  240. u32 id_revisionid;
  241. u32 ddrconf;
  242. u32 ddrtiming;
  243. u32 ddrmode;
  244. u32 readlatency;
  245. u32 activate;
  246. u32 devtodev;
  247. };
  248. struct rk322x_base_params {
  249. struct rk322x_msch_timings noc_timing;
  250. u32 ddrconfig;
  251. u32 ddr_freq;
  252. u32 dramtype;
  253. /*
  254. * unused for rk322x
  255. */
  256. u32 stride;
  257. u32 odt;
  258. };
  259. /* PCT_DFISTCFG0 */
  260. #define DFI_INIT_START BIT(0)
  261. #define DFI_DATA_BYTE_DISABLE_EN BIT(2)
  262. /* PCT_DFISTCFG1 */
  263. #define DFI_DRAM_CLK_SR_EN BIT(0)
  264. #define DFI_DRAM_CLK_DPD_EN BIT(1)
  265. /* PCT_DFISTCFG2 */
  266. #define DFI_PARITY_INTR_EN BIT(0)
  267. #define DFI_PARITY_EN BIT(1)
  268. /* PCT_DFILPCFG0 */
  269. #define TLP_RESP_TIME_SHIFT 16
  270. #define LP_SR_EN BIT(8)
  271. #define LP_PD_EN BIT(0)
  272. /* PCT_DFITCTRLDELAY */
  273. #define TCTRL_DELAY_TIME_SHIFT 0
  274. /* PCT_DFITPHYWRDATA */
  275. #define TPHY_WRDATA_TIME_SHIFT 0
  276. /* PCT_DFITPHYRDLAT */
  277. #define TPHY_RDLAT_TIME_SHIFT 0
  278. /* PCT_DFITDRAMCLKDIS */
  279. #define TDRAM_CLK_DIS_TIME_SHIFT 0
  280. /* PCT_DFITDRAMCLKEN */
  281. #define TDRAM_CLK_EN_TIME_SHIFT 0
  282. /* PCTL_DFIODTCFG */
  283. #define RANK0_ODT_WRITE_SEL BIT(3)
  284. #define RANK1_ODT_WRITE_SEL BIT(11)
  285. /* PCTL_DFIODTCFG1 */
  286. #define ODT_LEN_BL8_W_SHIFT 16
  287. /* PUBL_ACDLLCR */
  288. #define ACDLLCR_DLLDIS BIT(31)
  289. #define ACDLLCR_DLLSRST BIT(30)
  290. /* PUBL_DXDLLCR */
  291. #define DXDLLCR_DLLDIS BIT(31)
  292. #define DXDLLCR_DLLSRST BIT(30)
  293. /* PUBL_DLLGCR */
  294. #define DLLGCR_SBIAS BIT(30)
  295. /* PUBL_DXGCR */
  296. #define DQSRTT BIT(9)
  297. #define DQRTT BIT(10)
  298. /* PIR */
  299. #define PIR_INIT BIT(0)
  300. #define PIR_DLLSRST BIT(1)
  301. #define PIR_DLLLOCK BIT(2)
  302. #define PIR_ZCAL BIT(3)
  303. #define PIR_ITMSRST BIT(4)
  304. #define PIR_DRAMRST BIT(5)
  305. #define PIR_DRAMINIT BIT(6)
  306. #define PIR_QSTRN BIT(7)
  307. #define PIR_RVTRN BIT(8)
  308. #define PIR_ICPC BIT(16)
  309. #define PIR_DLLBYP BIT(17)
  310. #define PIR_CTLDINIT BIT(18)
  311. #define PIR_CLRSR BIT(28)
  312. #define PIR_LOCKBYP BIT(29)
  313. #define PIR_ZCALBYP BIT(30)
  314. #define PIR_INITBYP BIT(31)
  315. /* PGCR */
  316. #define PGCR_DFTLMT_SHIFT 3
  317. #define PGCR_DFTCMP_SHIFT 2
  318. #define PGCR_DQSCFG_SHIFT 1
  319. #define PGCR_ITMDMD_SHIFT 0
  320. /* PGSR */
  321. #define PGSR_IDONE BIT(0)
  322. #define PGSR_DLDONE BIT(1)
  323. #define PGSR_ZCDONE BIT(2)
  324. #define PGSR_DIDONE BIT(3)
  325. #define PGSR_DTDONE BIT(4)
  326. #define PGSR_DTERR BIT(5)
  327. #define PGSR_DTIERR BIT(6)
  328. #define PGSR_DFTERR BIT(7)
  329. #define PGSR_RVERR BIT(8)
  330. #define PGSR_RVEIRR BIT(9)
  331. /* PTR0 */
  332. #define PRT_ITMSRST_SHIFT 18
  333. #define PRT_DLLLOCK_SHIFT 6
  334. #define PRT_DLLSRST_SHIFT 0
  335. /* PTR1 */
  336. #define PRT_DINIT0_SHIFT 0
  337. #define PRT_DINIT1_SHIFT 19
  338. /* PTR2 */
  339. #define PRT_DINIT2_SHIFT 0
  340. #define PRT_DINIT3_SHIFT 17
  341. /* DCR */
  342. #define DDRMD_LPDDR 0
  343. #define DDRMD_DDR 1
  344. #define DDRMD_DDR2 2
  345. #define DDRMD_DDR3 3
  346. #define DDRMD_LPDDR2_LPDDR3 4
  347. #define DDRMD_MASK 7
  348. #define DDRMD_SHIFT 0
  349. #define PDQ_MASK 7
  350. #define PDQ_SHIFT 4
  351. /* DXCCR */
  352. #define DQSNRES_MASK 0xf
  353. #define DQSNRES_SHIFT 8
  354. #define DQSRES_MASK 0xf
  355. #define DQSRES_SHIFT 4
  356. /* DTPR */
  357. #define TDQSCKMAX_SHIFT 27
  358. #define TDQSCKMAX_MASK 7
  359. #define TDQSCK_SHIFT 24
  360. #define TDQSCK_MASK 7
  361. /* DSGCR */
  362. #define DQSGX_SHIFT 5
  363. #define DQSGX_MASK 7
  364. #define DQSGE_SHIFT 8
  365. #define DQSGE_MASK 7
  366. /* SCTL */
  367. #define INIT_STATE 0
  368. #define CFG_STATE 1
  369. #define GO_STATE 2
  370. #define SLEEP_STATE 3
  371. #define WAKEUP_STATE 4
  372. /* STAT */
  373. #define LP_TRIG_SHIFT 4
  374. #define LP_TRIG_MASK 7
  375. #define PCTL_STAT_MASK 7
  376. #define INIT_MEM 0
  377. #define CONFIG 1
  378. #define CONFIG_REQ 2
  379. #define ACCESS 3
  380. #define ACCESS_REQ 4
  381. #define LOW_POWER 5
  382. #define LOW_POWER_ENTRY_REQ 6
  383. #define LOW_POWER_EXIT_REQ 7
  384. /* ZQCR*/
  385. #define PD_OUTPUT_SHIFT 0
  386. #define PU_OUTPUT_SHIFT 5
  387. #define PD_ONDIE_SHIFT 10
  388. #define PU_ONDIE_SHIFT 15
  389. #define ZDEN_SHIFT 28
  390. /* DDLGCR */
  391. #define SBIAS_BYPASS BIT(23)
  392. /* MCFG */
  393. #define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
  394. #define PD_IDLE_SHIFT 8
  395. #define MDDR_EN (2 << 22)
  396. #define LPDDR2_EN (3 << 22)
  397. #define LPDDR3_EN (1 << 22)
  398. #define DDR2_EN (0 << 5)
  399. #define DDR3_EN (1 << 5)
  400. #define LPDDR2_S2 (0 << 6)
  401. #define LPDDR2_S4 (1 << 6)
  402. #define MDDR_LPDDR2_BL_2 (0 << 20)
  403. #define MDDR_LPDDR2_BL_4 (1 << 20)
  404. #define MDDR_LPDDR2_BL_8 (2 << 20)
  405. #define MDDR_LPDDR2_BL_16 (3 << 20)
  406. #define DDR2_DDR3_BL_4 0
  407. #define DDR2_DDR3_BL_8 1
  408. #define TFAW_SHIFT 18
  409. #define PD_EXIT_SLOW (0 << 17)
  410. #define PD_EXIT_FAST (1 << 17)
  411. #define PD_TYPE_SHIFT 16
  412. #define BURSTLENGTH_SHIFT 20
  413. /* POWCTL */
  414. #define POWER_UP_START BIT(0)
  415. /* POWSTAT */
  416. #define POWER_UP_DONE BIT(0)
  417. /* MCMD */
  418. enum {
  419. DESELECT_CMD = 0,
  420. PREA_CMD,
  421. REF_CMD,
  422. MRS_CMD,
  423. ZQCS_CMD,
  424. ZQCL_CMD,
  425. RSTL_CMD,
  426. MRR_CMD = 8,
  427. DPDE_CMD,
  428. };
  429. #define BANK_ADDR_MASK 7
  430. #define BANK_ADDR_SHIFT 17
  431. #define CMD_ADDR_MASK 0x1fff
  432. #define CMD_ADDR_SHIFT 4
  433. #define LPDDR23_MA_SHIFT 4
  434. #define LPDDR23_MA_MASK 0xff
  435. #define LPDDR23_OP_SHIFT 12
  436. #define LPDDR23_OP_MASK 0xff
  437. #define START_CMD (1u << 31)
  438. /* DDRPHY REG */
  439. enum {
  440. /* DDRPHY_REG0 */
  441. SOFT_RESET_MASK = 3,
  442. SOFT_DERESET_ANALOG = 1 << 2,
  443. SOFT_DERESET_DIGITAL = 1 << 3,
  444. SOFT_RESET_SHIFT = 2,
  445. /* DDRPHY REG1 */
  446. PHY_DDR3 = 0,
  447. PHY_DDR2 = 1,
  448. PHY_LPDDR3 = 2,
  449. PHY_LPDDR2 = 3,
  450. PHT_BL_8 = 1 << 2,
  451. PHY_BL_4 = 0 << 2,
  452. /* DDRPHY_REG2 */
  453. MEMORY_SELECT_DDR3 = 0 << 0,
  454. MEMORY_SELECT_LPDDR3 = 2 << 0,
  455. MEMORY_SELECT_LPDDR2 = 3 << 0,
  456. DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4,
  457. DQS_SQU_CAL_SEL_CS1 = 1 << 4,
  458. DQS_SQU_CAL_SEL_CS0 = 2 << 4,
  459. DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
  460. DQS_SQU_CAL_BYPASS_MODE = 1 << 1,
  461. DQS_SQU_CAL_START = 1 << 0,
  462. DQS_SQU_NO_CAL = 0 << 0,
  463. };
  464. /* CK pull up/down driver strength control */
  465. enum {
  466. PHY_RON_RTT_DISABLE = 0,
  467. PHY_RON_RTT_451OHM = 1,
  468. PHY_RON_RTT_225OHM,
  469. PHY_RON_RTT_150OHM,
  470. PHY_RON_RTT_112OHM,
  471. PHY_RON_RTT_90OHM,
  472. PHY_RON_RTT_75OHM,
  473. PHY_RON_RTT_64OHM = 7,
  474. PHY_RON_RTT_56OHM = 16,
  475. PHY_RON_RTT_50OHM,
  476. PHY_RON_RTT_45OHM,
  477. PHY_RON_RTT_41OHM,
  478. PHY_RON_RTT_37OHM,
  479. PHY_RON_RTT_34OHM,
  480. PHY_RON_RTT_33OHM,
  481. PHY_RON_RTT_30OHM = 23,
  482. PHY_RON_RTT_28OHM = 24,
  483. PHY_RON_RTT_26OHM,
  484. PHY_RON_RTT_25OHM,
  485. PHY_RON_RTT_23OHM,
  486. PHY_RON_RTT_22OHM,
  487. PHY_RON_RTT_21OHM,
  488. PHY_RON_RTT_20OHM,
  489. PHY_RON_RTT_19OHM = 31,
  490. };
  491. /* DQS squelch DLL delay */
  492. enum {
  493. DQS_DLL_NO_DELAY = 0,
  494. DQS_DLL_22P5_DELAY,
  495. DQS_DLL_45_DELAY,
  496. DQS_DLL_67P5_DELAY,
  497. DQS_DLL_90_DELAY,
  498. DQS_DLL_112P5_DELAY,
  499. DQS_DLL_135_DELAY,
  500. DQS_DLL_157P5_DELAY,
  501. };
  502. /* GRF_SOC_CON0 */
  503. #define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0))
  504. #define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0))
  505. #define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7))
  506. #define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7))
  507. #define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8))
  508. #define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8))
  509. #define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6))
  510. #define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6))
  511. #define PHY_DRV_ODT_SET(n) (((n) << 4) | (n))
  512. #define DDR3_DLL_RESET (1 << 8)
  513. #endif /* _ASM_ARCH_SDRAM_RK322X_H */