cru_rv1108.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  4. * Author: Andy Yan <andy.yan@rock-chips.com>
  5. */
  6. #ifndef _ASM_ARCH_CRU_RV1108_H
  7. #define _ASM_ARCH_CRU_RV1108_H
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. #define OSC_HZ (24 * 1000 * 1000)
  12. #define APLL_HZ (600 * 1000000)
  13. #define GPLL_HZ (1188 * 1000000)
  14. #define ACLK_PERI_HZ (148500000)
  15. #define HCLK_PERI_HZ (148500000)
  16. #define PCLK_PERI_HZ (74250000)
  17. #define ACLK_BUS_HZ (148500000)
  18. struct rv1108_clk_priv {
  19. struct rv1108_cru *cru;
  20. ulong rate;
  21. };
  22. struct rv1108_cru {
  23. struct rv1108_pll {
  24. unsigned int con0;
  25. unsigned int con1;
  26. unsigned int con2;
  27. unsigned int con3;
  28. unsigned int con4;
  29. unsigned int con5;
  30. unsigned int reserved[2];
  31. } pll[3];
  32. unsigned int clksel_con[46];
  33. unsigned int reserved1[2];
  34. unsigned int clkgate_con[20];
  35. unsigned int reserved2[4];
  36. unsigned int softrst_con[13];
  37. unsigned int reserved3[3];
  38. unsigned int glb_srst_fst_val;
  39. unsigned int glb_srst_snd_val;
  40. unsigned int glb_cnt_th;
  41. unsigned int misc_con;
  42. unsigned int glb_rst_con;
  43. unsigned int glb_rst_st;
  44. unsigned int sdmmc_con[2];
  45. unsigned int sdio_con[2];
  46. unsigned int emmc_con[2];
  47. };
  48. check_member(rv1108_cru, emmc_con[1], 0x01ec);
  49. struct pll_div {
  50. u32 refdiv;
  51. u32 fbdiv;
  52. u32 postdiv1;
  53. u32 postdiv2;
  54. u32 frac;
  55. };
  56. enum {
  57. /* PLL CON0 */
  58. FBDIV_MASK = 0xfff,
  59. FBDIV_SHIFT = 0,
  60. /* PLL CON1 */
  61. POSTDIV2_SHIFT = 12,
  62. POSTDIV2_MASK = 7 << POSTDIV2_SHIFT,
  63. POSTDIV1_SHIFT = 8,
  64. POSTDIV1_MASK = 7 << POSTDIV1_SHIFT,
  65. REFDIV_MASK = 0x3f,
  66. REFDIV_SHIFT = 0,
  67. /* PLL CON2 */
  68. LOCK_STA_SHIFT = 31,
  69. LOCK_STA_MASK = 1 << LOCK_STA_SHIFT,
  70. FRACDIV_MASK = 0xffffff,
  71. FRACDIV_SHIFT = 0,
  72. /* PLL CON3 */
  73. WORK_MODE_SHIFT = 8,
  74. WORK_MODE_MASK = 1 << WORK_MODE_SHIFT,
  75. WORK_MODE_SLOW = 0,
  76. WORK_MODE_NORMAL = 1,
  77. DSMPD_SHIFT = 3,
  78. DSMPD_MASK = 1 << DSMPD_SHIFT,
  79. INTEGER_MODE = 1,
  80. GLOBAL_POWER_DOWN_SHIFT = 0,
  81. GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT,
  82. GLOBAL_POWER_DOWN = 1,
  83. GLOBAL_POWER_UP = 0,
  84. /* CLKSEL0_CON */
  85. CORE_PLL_SEL_SHIFT = 8,
  86. CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT,
  87. CORE_PLL_SEL_APLL = 0,
  88. CORE_PLL_SEL_GPLL = 1,
  89. CORE_PLL_SEL_DPLL = 2,
  90. CORE_CLK_DIV_SHIFT = 0,
  91. CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT,
  92. /* CLKSEL_CON1 */
  93. PCLK_DBG_DIV_CON_SHIFT = 4,
  94. PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT,
  95. ACLK_CORE_DIV_CON_SHIFT = 0,
  96. ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT,
  97. /* CLKSEL_CON2 */
  98. ACLK_BUS_PLL_SEL_SHIFT = 8,
  99. ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT,
  100. ACLK_BUS_PLL_SEL_GPLL = 0,
  101. ACLK_BUS_PLL_SEL_APLL = 1,
  102. ACLK_BUS_PLL_SEL_DPLL = 2,
  103. ACLK_BUS_DIV_CON_SHIFT = 0,
  104. ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT,
  105. ACLK_BUS_DIV_CON_WIDTH = 5,
  106. /* CLKSEL_CON3 */
  107. PCLK_BUS_DIV_CON_SHIFT = 8,
  108. PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT,
  109. HCLK_BUS_DIV_CON_SHIFT = 0,
  110. HCLK_BUS_DIV_CON_MASK = 0x1f,
  111. /* CLKSEL_CON4 */
  112. CLK_DDR_PLL_SEL_SHIFT = 8,
  113. CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT,
  114. CLK_DDR_DIV_CON_SHIFT = 0,
  115. CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT,
  116. /* CLKSEL_CON19 */
  117. CLK_I2C1_PLL_SEL_SHIFT = 15,
  118. CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT,
  119. CLK_I2C1_PLL_SEL_DPLL = 0,
  120. CLK_I2C1_PLL_SEL_GPLL = 1,
  121. CLK_I2C1_DIV_CON_SHIFT = 8,
  122. CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT,
  123. CLK_I2C0_PLL_SEL_SHIFT = 7,
  124. CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT,
  125. CLK_I2C0_DIV_CON_SHIFT = 0,
  126. CLK_I2C0_DIV_CON_MASK = 0x7f,
  127. I2C_DIV_CON_WIDTH = 7,
  128. /* CLKSEL_CON20 */
  129. CLK_I2C3_PLL_SEL_SHIFT = 15,
  130. CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT,
  131. CLK_I2C3_PLL_SEL_DPLL = 0,
  132. CLK_I2C3_PLL_SEL_GPLL = 1,
  133. CLK_I2C3_DIV_CON_SHIFT = 8,
  134. CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT,
  135. CLK_I2C2_PLL_SEL_SHIFT = 7,
  136. CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT,
  137. CLK_I2C2_DIV_CON_SHIFT = 0,
  138. CLK_I2C2_DIV_CON_MASK = 0x7f,
  139. /* CLKSEL_CON22 */
  140. CLK_SARADC_DIV_CON_SHIFT= 0,
  141. CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
  142. CLK_SARADC_DIV_CON_WIDTH= 10,
  143. /* CLKSEL_CON23 */
  144. ACLK_PERI_PLL_SEL_SHIFT = 15,
  145. ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT,
  146. ACLK_PERI_PLL_SEL_GPLL = 0,
  147. ACLK_PERI_PLL_SEL_DPLL = 1,
  148. PCLK_PERI_DIV_CON_SHIFT = 10,
  149. PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT,
  150. HCLK_PERI_DIV_CON_SHIFT = 5,
  151. HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT,
  152. ACLK_PERI_DIV_CON_SHIFT = 0,
  153. ACLK_PERI_DIV_CON_MASK = 0x1f,
  154. PERI_DIV_CON_WIDTH = 5,
  155. /* CLKSEL24_CON */
  156. MAC_PLL_SEL_SHIFT = 12,
  157. MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
  158. MAC_PLL_SEL_APLL = 0,
  159. MAC_PLL_SEL_GPLL = 1,
  160. RMII_EXTCLK_SEL_SHIFT = 8,
  161. RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT,
  162. MAC_CLK_DIV_MASK = 0x1f,
  163. MAC_CLK_DIV_SHIFT = 0,
  164. /* CLKSEL25_CON */
  165. EMMC_PLL_SEL_SHIFT = 12,
  166. EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT,
  167. EMMC_PLL_SEL_DPLL = 0,
  168. EMMC_PLL_SEL_GPLL,
  169. EMMC_PLL_SEL_OSC,
  170. /* CLKSEL26_CON */
  171. EMMC_CLK_DIV_SHIFT = 8,
  172. EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT,
  173. /* CLKSEL27_CON */
  174. SFC_PLL_SEL_SHIFT = 7,
  175. SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT,
  176. SFC_PLL_SEL_DPLL = 0,
  177. SFC_PLL_SEL_GPLL = 1,
  178. SFC_CLK_DIV_SHIFT = 0,
  179. SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT,
  180. /* CLKSEL28_CON */
  181. ACLK_VIO1_PLL_SEL_SHIFT = 14,
  182. ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT,
  183. VIO_PLL_SEL_DPLL = 0,
  184. VIO_PLL_SEL_GPLL = 1,
  185. ACLK_VIO1_CLK_DIV_SHIFT = 8,
  186. ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT,
  187. CLK_VIO_DIV_CON_WIDTH = 5,
  188. ACLK_VIO0_PLL_SEL_SHIFT = 6,
  189. ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT,
  190. ACLK_VIO0_CLK_DIV_SHIFT = 0,
  191. ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT,
  192. /* CLKSEL29_CON */
  193. PCLK_VIO_CLK_DIV_SHIFT = 8,
  194. PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT,
  195. HCLK_VIO_CLK_DIV_SHIFT = 0,
  196. HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT,
  197. /* CLKSEL32_CON */
  198. DCLK_VOP_SEL_SHIFT = 7,
  199. DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
  200. DCLK_VOP_SEL_HDMI = 0,
  201. DCLK_VOP_SEL_PLL = 1,
  202. DCLK_VOP_PLL_SEL_SHIFT = 6,
  203. DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT,
  204. DCLK_VOP_PLL_SEL_GPLL = 0,
  205. DCLK_VOP_PLL_SEL_DPLL = 1,
  206. DCLK_VOP_CLK_DIV_SHIFT = 0,
  207. DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT,
  208. DCLK_VOP_DIV_CON_WIDTH = 6,
  209. /* SOFTRST1_CON*/
  210. DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0,
  211. DDRPHY_SRSTN_CLKDIV_REQ = 1,
  212. DDRPHY_SRSTN_CLKDIV_DIS = 0,
  213. DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT,
  214. DDRPHY_SRSTN_REQ_SHIFT = 1,
  215. DDRPHY_SRSTN_REQ = 1,
  216. DDRPHY_SRSTN_DIS = 0,
  217. DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT,
  218. DDRPHY_PSRSTN_REQ_SHIFT = 2,
  219. DDRPHY_PSRSTN_REQ = 1,
  220. DDRPHY_PSRSTN_DIS = 0,
  221. DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT,
  222. /* SOFTRST2_CON*/
  223. DDRUPCTL_PSRSTN_REQ_SHIFT = 0,
  224. DDRUPCTL_PSRSTN_REQ = 1,
  225. DDRUPCTL_PSRSTN_DIS = 0,
  226. DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT,
  227. DDRUPCTL_NSRSTN_REQ_SHIFT = 1,
  228. DDRUPCTL_NSRSTN_REQ = 1,
  229. DDRUPCTL_NSRSTN_DIS = 0,
  230. DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT,
  231. };
  232. #endif