cru_rk3368.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. * Author: Andy Yan <andy.yan@rock-chips.com>
  5. */
  6. #ifndef _ASM_ARCH_CRU_RK3368_H
  7. #define _ASM_ARCH_CRU_RK3368_H
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. /* RK3368 clock numbers */
  12. enum rk3368_pll_id {
  13. APLLB,
  14. APLLL,
  15. DPLL,
  16. CPLL,
  17. GPLL,
  18. NPLL,
  19. PLL_COUNT,
  20. };
  21. struct rk3368_cru {
  22. struct rk3368_pll {
  23. unsigned int con0;
  24. unsigned int con1;
  25. unsigned int con2;
  26. unsigned int con3;
  27. } pll[6];
  28. unsigned int reserved[0x28];
  29. unsigned int clksel_con[56];
  30. unsigned int reserved1[8];
  31. unsigned int clkgate_con[25];
  32. unsigned int reserved2[7];
  33. unsigned int glb_srst_fst_val;
  34. unsigned int glb_srst_snd_val;
  35. unsigned int reserved3[0x1e];
  36. unsigned int softrst_con[15];
  37. unsigned int reserved4[0x11];
  38. unsigned int misc_con;
  39. unsigned int glb_cnt_th;
  40. unsigned int glb_rst_con;
  41. unsigned int glb_rst_st;
  42. unsigned int reserved5[0x1c];
  43. unsigned int sdmmc_con[2];
  44. unsigned int sdio0_con[2];
  45. unsigned int sdio1_con[2];
  46. unsigned int emmc_con[2];
  47. };
  48. check_member(rk3368_cru, emmc_con[1], 0x41c);
  49. struct rk3368_clk_priv {
  50. struct rk3368_cru *cru;
  51. };
  52. enum {
  53. /* PLL CON0 */
  54. PLL_NR_SHIFT = 8,
  55. PLL_NR_MASK = GENMASK(13, 8),
  56. PLL_OD_SHIFT = 0,
  57. PLL_OD_MASK = GENMASK(3, 0),
  58. /* PLL CON1 */
  59. PLL_LOCK_STA = BIT(31),
  60. PLL_NF_SHIFT = 0,
  61. PLL_NF_MASK = GENMASK(12, 0),
  62. /* PLL CON2 */
  63. PLL_BWADJ_SHIFT = 0,
  64. PLL_BWADJ_MASK = GENMASK(11, 0),
  65. /* PLL CON3 */
  66. PLL_MODE_SHIFT = 8,
  67. PLL_MODE_MASK = GENMASK(9, 8),
  68. PLL_MODE_SLOW = 0,
  69. PLL_MODE_NORMAL = 1,
  70. PLL_MODE_DEEP_SLOW = 3,
  71. PLL_RESET_SHIFT = 5,
  72. PLL_RESET = 1,
  73. PLL_RESET_MASK = GENMASK(5, 5),
  74. /* CLKSEL12_CON */
  75. MCU_STCLK_DIV_SHIFT = 8,
  76. MCU_STCLK_DIV_MASK = GENMASK(10, 8),
  77. MCU_PLL_SEL_SHIFT = 7,
  78. MCU_PLL_SEL_MASK = BIT(7),
  79. MCU_PLL_SEL_CPLL = 0,
  80. MCU_PLL_SEL_GPLL = 1,
  81. MCU_CLK_DIV_SHIFT = 0,
  82. MCU_CLK_DIV_MASK = GENMASK(4, 0),
  83. /* CLKSEL_CON25 */
  84. CLK_SARADC_DIV_CON_SHIFT = 8,
  85. CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
  86. CLK_SARADC_DIV_CON_WIDTH = 8,
  87. /* CLKSEL43_CON */
  88. GMAC_DIV_CON_SHIFT = 0x0,
  89. GMAC_DIV_CON_MASK = GENMASK(4, 0),
  90. GMAC_PLL_SHIFT = 6,
  91. GMAC_PLL_MASK = GENMASK(7, 6),
  92. GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
  93. GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT),
  94. GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
  95. GMAC_MUX_SEL_EXTCLK = BIT(8),
  96. /* CLKSEL51_CON */
  97. MMC_PLL_SEL_SHIFT = 8,
  98. MMC_PLL_SEL_MASK = GENMASK(9, 8),
  99. MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
  100. MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
  101. MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
  102. MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
  103. MMC_CLK_DIV_SHIFT = 0,
  104. MMC_CLK_DIV_MASK = GENMASK(6, 0),
  105. /* SOFTRST1_CON */
  106. MCU_PO_SRST_MASK = BIT(13),
  107. MCU_SYS_SRST_MASK = BIT(12),
  108. DMA1_SRST_REQ = BIT(2),
  109. /* SOFTRST4_CON */
  110. DMA2_SRST_REQ = BIT(0),
  111. /* GLB_RST_CON */
  112. PMU_GLB_SRST_CTRL_SHIFT = 2,
  113. PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
  114. PMU_RST_BY_FST_GLB_SRST = 0,
  115. PMU_RST_BY_SND_GLB_SRST = 1,
  116. PMU_RST_DISABLE = 2,
  117. WDT_GLB_SRST_CTRL_SHIFT = 1,
  118. WDT_GLB_SRST_CTRL_MASK = BIT(1),
  119. WDT_TRIGGER_SND_GLB_SRST = 0,
  120. WDT_TRIGGER_FST_GLB_SRST = 1,
  121. TSADC_GLB_SRST_CTRL_SHIFT = 0,
  122. TSADC_GLB_SRST_CTRL_MASK = BIT(0),
  123. TSADC_TRIGGER_SND_GLB_SRST = 0,
  124. TSADC_TRIGGER_FST_GLB_SRST = 1,
  125. };
  126. #endif