cru_rk3128.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #ifndef _ASM_ARCH_CRU_RK3128_H
  6. #define _ASM_ARCH_CRU_RK3128_H
  7. #ifndef __ASSEMBLY__
  8. #include <linux/bitops.h>
  9. #endif
  10. #define MHz 1000000
  11. #define OSC_HZ (24 * MHz)
  12. #define APLL_HZ (600 * MHz)
  13. #define GPLL_HZ (594 * MHz)
  14. #define CORE_PERI_HZ 150000000
  15. #define CORE_ACLK_HZ 300000000
  16. #define BUS_ACLK_HZ 148500000
  17. #define BUS_HCLK_HZ 148500000
  18. #define BUS_PCLK_HZ 74250000
  19. #define PERI_ACLK_HZ 148500000
  20. #define PERI_HCLK_HZ 148500000
  21. #define PERI_PCLK_HZ 74250000
  22. /* Private data for the clock driver - used by rockchip_get_cru() */
  23. struct rk3128_clk_priv {
  24. struct rk3128_cru *cru;
  25. };
  26. struct rk3128_cru {
  27. struct rk3128_pll {
  28. unsigned int con0;
  29. unsigned int con1;
  30. unsigned int con2;
  31. unsigned int con3;
  32. } pll[4];
  33. unsigned int cru_mode_con;
  34. unsigned int cru_clksel_con[35];
  35. unsigned int cru_clkgate_con[11];
  36. unsigned int reserved;
  37. unsigned int cru_glb_srst_fst_value;
  38. unsigned int cru_glb_srst_snd_value;
  39. unsigned int reserved1[2];
  40. unsigned int cru_softrst_con[9];
  41. unsigned int cru_misc_con;
  42. unsigned int reserved2[2];
  43. unsigned int cru_glb_cnt_th;
  44. unsigned int reserved3[3];
  45. unsigned int cru_glb_rst_st;
  46. unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
  47. unsigned int cru_sdmmc_con[2];
  48. unsigned int cru_sdio_con[2];
  49. unsigned int reserved5[2];
  50. unsigned int cru_emmc_con[2];
  51. unsigned int reserved6[4];
  52. unsigned int cru_pll_prg_en;
  53. };
  54. check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
  55. struct pll_div {
  56. u32 refdiv;
  57. u32 fbdiv;
  58. u32 postdiv1;
  59. u32 postdiv2;
  60. u32 frac;
  61. };
  62. enum {
  63. /* PLLCON0*/
  64. PLL_POSTDIV1_SHIFT = 12,
  65. PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
  66. PLL_FBDIV_SHIFT = 0,
  67. PLL_FBDIV_MASK = 0xfff,
  68. /* PLLCON1 */
  69. PLL_RST_SHIFT = 14,
  70. PLL_PD_SHIFT = 13,
  71. PLL_PD_MASK = 1 << PLL_PD_SHIFT,
  72. PLL_DSMPD_SHIFT = 12,
  73. PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
  74. PLL_LOCK_STATUS_SHIFT = 10,
  75. PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
  76. PLL_POSTDIV2_SHIFT = 6,
  77. PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
  78. PLL_REFDIV_SHIFT = 0,
  79. PLL_REFDIV_MASK = 0x3f,
  80. /* CRU_MODE */
  81. GPLL_MODE_SHIFT = 12,
  82. GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
  83. GPLL_MODE_SLOW = 0,
  84. GPLL_MODE_NORM,
  85. GPLL_MODE_DEEP,
  86. CPLL_MODE_SHIFT = 8,
  87. CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
  88. CPLL_MODE_SLOW = 0,
  89. CPLL_MODE_NORM,
  90. DPLL_MODE_SHIFT = 4,
  91. DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
  92. DPLL_MODE_SLOW = 0,
  93. DPLL_MODE_NORM,
  94. APLL_MODE_SHIFT = 0,
  95. APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
  96. APLL_MODE_SLOW = 0,
  97. APLL_MODE_NORM,
  98. /* CRU_CLK_SEL0_CON */
  99. BUS_ACLK_PLL_SEL_SHIFT = 14,
  100. BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
  101. BUS_ACLK_PLL_SEL_CPLL = 0,
  102. BUS_ACLK_PLL_SEL_GPLL,
  103. BUS_ACLK_PLL_SEL_GPLL_DIV2,
  104. BUS_ACLK_PLL_SEL_GPLL_DIV3,
  105. BUS_ACLK_DIV_SHIFT = 8,
  106. BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
  107. CORE_CLK_PLL_SEL_SHIFT = 7,
  108. CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
  109. CORE_CLK_PLL_SEL_APLL = 0,
  110. CORE_CLK_PLL_SEL_GPLL_DIV2,
  111. CORE_DIV_CON_SHIFT = 0,
  112. CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
  113. /* CRU_CLK_SEL1_CON */
  114. BUS_PCLK_DIV_SHIFT = 12,
  115. BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
  116. BUS_HCLK_DIV_SHIFT = 8,
  117. BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
  118. CORE_ACLK_DIV_SHIFT = 4,
  119. CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
  120. CORE_PERI_DIV_SHIFT = 0,
  121. CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
  122. /* CRU_CLK_SEL2_CON */
  123. NANDC_PLL_SEL_SHIFT = 14,
  124. NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT,
  125. NANDC_PLL_SEL_CPLL = 0,
  126. NANDC_PLL_SEL_GPLL,
  127. NANDC_CLK_DIV_SHIFT = 8,
  128. NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT,
  129. PVTM_CLK_DIV_SHIFT = 0,
  130. PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT,
  131. /* CRU_CLKSEL10_CON */
  132. PERI_PLL_SEL_SHIFT = 14,
  133. PERI_PLL_SEL_MASK = 1 << PERI_PLL_SEL_SHIFT,
  134. PERI_PLL_APLL = 0,
  135. PERI_PLL_DPLL,
  136. PERI_PLL_GPLL,
  137. PERI_PCLK_DIV_SHIFT = 12,
  138. PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
  139. PERI_HCLK_DIV_SHIFT = 8,
  140. PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
  141. PERI_ACLK_DIV_SHIFT = 0,
  142. PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
  143. /* CRU_CLKSEL11_CON */
  144. MMC0_PLL_SHIFT = 6,
  145. MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
  146. MMC0_SEL_APLL = 0,
  147. MMC0_SEL_GPLL,
  148. MMC0_SEL_GPLL_DIV2,
  149. MMC0_SEL_24M,
  150. MMC0_DIV_SHIFT = 0,
  151. MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
  152. /* CRU_CLKSEL12_CON */
  153. EMMC_PLL_SHIFT = 14,
  154. EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
  155. EMMC_SEL_APLL = 0,
  156. EMMC_SEL_GPLL,
  157. EMMC_SEL_GPLL_DIV2,
  158. EMMC_SEL_24M,
  159. EMMC_DIV_SHIFT = 8,
  160. EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
  161. /* CLKSEL_CON24 */
  162. SARADC_DIV_CON_SHIFT = 8,
  163. SARADC_DIV_CON_MASK = GENMASK(15, 8),
  164. SARADC_DIV_CON_WIDTH = 8,
  165. /* CRU_CLKSEL27_CON*/
  166. DCLK_VOP_SEL_SHIFT = 0,
  167. DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
  168. DCLK_VOP_PLL_SEL_CPLL = 0,
  169. DCLK_VOP_DIV_CON_SHIFT = 8,
  170. DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
  171. /* CRU_CLKSEL31_CON */
  172. VIO0_PLL_SHIFT = 5,
  173. VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT,
  174. VI00_SEL_CPLL = 0,
  175. VIO0_SEL_GPLL,
  176. VIO0_DIV_SHIFT = 0,
  177. VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT,
  178. VIO1_PLL_SHIFT = 13,
  179. VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT,
  180. VI01_SEL_CPLL = 0,
  181. VIO1_SEL_GPLL,
  182. VIO1_DIV_SHIFT = 8,
  183. VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT,
  184. /* CRU_SOFTRST5_CON */
  185. DDRCTRL_PSRST_SHIFT = 11,
  186. DDRCTRL_SRST_SHIFT = 10,
  187. DDRPHY_PSRST_SHIFT = 9,
  188. DDRPHY_SRST_SHIFT = 8,
  189. };
  190. #endif