gx.h 1.9 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
  4. */
  5. #ifndef __GX_H__
  6. #define __GX_H__
  7. #ifndef __ASSEMBLY__
  8. #include <linux/bitops.h>
  9. #endif
  10. #define GX_FIRMWARE_MEM_SIZE 0x1000000
  11. #define GX_AOBUS_BASE 0xc8100000
  12. #define GX_PERIPHS_BASE 0xc8834400
  13. #define GX_HIU_BASE 0xc883c000
  14. #define GX_ETH_BASE 0xc9410000
  15. /* Always-On Peripherals registers */
  16. #define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2))
  17. #define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90)
  18. #define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93)
  19. #define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)
  20. #define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95)
  21. #define GX_AO_BOOT_DEVICE 0xF
  22. #define GX_AO_MEM_SIZE_MASK 0xFFFF0000
  23. #define GX_AO_MEM_SIZE_SHIFT 16
  24. #define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
  25. #define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16
  26. #define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
  27. /* Peripherals registers */
  28. #define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2))
  29. /* GPIO registers 0 to 6 */
  30. #define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
  31. #define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0)
  32. #define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
  33. #define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
  34. #define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50)
  35. #define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51)
  36. #define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56)
  37. #define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57)
  38. #define GX_ETH_REG_0_PHY_INTF BIT(0)
  39. #define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
  40. #define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
  41. #define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
  42. #define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
  43. #define GX_ETH_REG_0_CLK_EN BIT(12)
  44. /* HIU registers */
  45. #define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2))
  46. #define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40)
  47. /* Ethernet memory power domain */
  48. #define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
  49. #endif /* __GX_H__ */