clock_imx8mm.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #ifndef _ASM_ARCH_IMX8MM_CLOCK_H
  8. #define _ASM_ARCH_IMX8MM_CLOCK_H
  9. #ifndef __ASSEMBLY__
  10. #include <linux/bitops.h>
  11. #endif
  12. #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
  13. { \
  14. .rate = (_rate), \
  15. .mdiv = (_m), \
  16. .pdiv = (_p), \
  17. .sdiv = (_s), \
  18. .kdiv = (_k), \
  19. }
  20. #define LOCK_STATUS BIT(31)
  21. #define LOCK_SEL_MASK BIT(29)
  22. #define CLKE_MASK BIT(13)
  23. #define RST_MASK BIT(9)
  24. #define BYPASS_MASK BIT(4)
  25. #define MDIV_SHIFT 12
  26. #define MDIV_MASK GENMASK(21, 12)
  27. #define PDIV_SHIFT 4
  28. #define PDIV_MASK GENMASK(9, 4)
  29. #define SDIV_SHIFT 0
  30. #define SDIV_MASK GENMASK(2, 0)
  31. #define KDIV_SHIFT 0
  32. #define KDIV_MASK GENMASK(15, 0)
  33. struct imx_int_pll_rate_table {
  34. u32 rate;
  35. int mdiv;
  36. int pdiv;
  37. int sdiv;
  38. int kdiv;
  39. };
  40. enum pll_clocks {
  41. ANATOP_ARM_PLL,
  42. ANATOP_VPU_PLL,
  43. ANATOP_GPU_PLL,
  44. ANATOP_SYSTEM_PLL1,
  45. ANATOP_SYSTEM_PLL2,
  46. ANATOP_SYSTEM_PLL3,
  47. ANATOP_AUDIO_PLL1,
  48. ANATOP_AUDIO_PLL2,
  49. ANATOP_VIDEO_PLL,
  50. ANATOP_DRAM_PLL,
  51. };
  52. #ifdef CONFIG_IMX8MP
  53. enum clk_root_index {
  54. ARM_A53_CLK_ROOT = 0,
  55. ARM_M7_CLK_ROOT = 1,
  56. ML_CLK_ROOT = 2,
  57. GPU3D_CORE_CLK_ROOT = 3,
  58. GPU3D_SHADER_CLK_ROOT = 4,
  59. GPU2D_CLK_ROOT = 5,
  60. AUDIO_AXI_CLK_ROOT = 6,
  61. HSIO_AXI_CLK_ROOT = 7,
  62. MEDIA_ISP_CLK_ROOT = 8,
  63. MAIN_AXI_CLK_ROOT = 16,
  64. ENET_AXI_CLK_ROOT = 17,
  65. NAND_USDHC_BUS_CLK_ROOT = 18,
  66. VPU_BUS_CLK_ROOT = 19,
  67. MEDIA_AXI_CLK_ROOT = 20,
  68. MEDIA_APB_CLK_ROOT = 21,
  69. HDMI_APB_CLK_ROOT = 22,
  70. HDMI_AXI_CLK_ROOT = 23,
  71. GPU_AXI_CLK_ROOT = 24,
  72. GPU_AHB_CLK_ROOT = 25,
  73. NOC_CLK_ROOT = 26,
  74. NOC_IO_CLK_ROOT = 27,
  75. ML_AXI_CLK_ROOT = 28,
  76. ML_AHB_CLK_ROOT = 29,
  77. AHB_CLK_ROOT = 32,
  78. IPG_CLK_ROOT = 33,
  79. AUDIO_AHB_CLK_ROOT = 34,
  80. MIPI_DSI_ESC_RX_CLK_ROOT = 36,
  81. MEDIA_DISP2_CLK_ROOT = 38,
  82. DRAM_SEL_CFG = 48,
  83. CORE_SEL_CFG = 49,
  84. DRAM_ALT_CLK_ROOT = 64,
  85. DRAM_APB_CLK_ROOT = 65,
  86. VPU_G1_CLK_ROOT = 66,
  87. VPU_G2_CLK_ROOT = 67,
  88. CAN1_CLK_ROOT = 68,
  89. CAN2_CLK_ROOT = 69,
  90. PCIE_PHY_CLK_ROOT = 71,
  91. PCIE_AUX_CLK_ROOT = 72,
  92. I2C5_CLK_ROOT = 73,
  93. I2C6_CLK_ROOT = 74,
  94. SAI1_CLK_ROOT = 75,
  95. SAI2_CLK_ROOT = 76,
  96. SAI3_CLK_ROOT = 77,
  97. SAI4_CLK_ROOT = 78,
  98. SAI5_CLK_ROOT = 79,
  99. SAI6_CLK_ROOT = 80,
  100. ENET_QOS_CLK_ROOT = 81,
  101. ENET_QOS_TIMER_CLK_ROOT = 82,
  102. ENET_REF_CLK_ROOT = 83,
  103. ENET_TIMER_CLK_ROOT = 84,
  104. ENET_PHY_REF_CLK_ROOT = 85,
  105. NAND_CLK_ROOT = 86,
  106. QSPI_CLK_ROOT = 87,
  107. USDHC1_CLK_ROOT = 88,
  108. USDHC2_CLK_ROOT = 89,
  109. I2C1_CLK_ROOT = 90,
  110. I2C2_CLK_ROOT = 91,
  111. I2C3_CLK_ROOT = 92,
  112. I2C4_CLK_ROOT = 93,
  113. UART1_CLK_ROOT = 94,
  114. UART2_CLK_ROOT = 95,
  115. UART3_CLK_ROOT = 96,
  116. UART4_CLK_ROOT = 97,
  117. USB_CORE_REF_CLK_ROOT = 98,
  118. USB_PHY_REF_CLK_ROOT = 99,
  119. GIC_CLK_ROOT = 100,
  120. ECSPI1_CLK_ROOT = 101,
  121. ECSPI2_CLK_ROOT = 102,
  122. PWM1_CLK_ROOT = 103,
  123. PWM2_CLK_ROOT = 104,
  124. PWM3_CLK_ROOT = 105,
  125. PWM4_CLK_ROOT = 106,
  126. GPT1_CLK_ROOT = 107,
  127. GPT2_CLK_ROOT = 108,
  128. GPT3_CLK_ROOT = 109,
  129. GPT4_CLK_ROOT = 110,
  130. GPT5_CLK_ROOT = 111,
  131. GPT6_CLK_ROOT = 112,
  132. TRACE_CLK_ROOT = 113,
  133. WDOG_CLK_ROOT = 114,
  134. WRCLK_CLK_ROOT = 115,
  135. IPP_DO_CLKO1 = 116,
  136. IPP_DO_CLKO2 = 117,
  137. HDMI_FDCC_TST_CLK_ROOT = 118,
  138. HDMI_27M_CLK_ROOT = 119,
  139. HDMI_REF_266M_CLK_ROOT = 120,
  140. USDHC3_CLK_ROOT = 121,
  141. MEDIA_CAM1_PIX_CLK_ROOT = 122,
  142. MEDIA_MIPI_PHY1_REF_CLK_ROOT = 123,
  143. MEDIA_DISP1_PIX_CLK_ROOT = 124,
  144. MEDIA_CAM2_PIX_CLK_ROOT = 125,
  145. MEDIA_LDB_CLK_ROOT = 126,
  146. MEMREPAIR_CLK_ROOT = 127,
  147. MEDIA_MIPI_TEST_BYTE_CLK = 130,
  148. ECSPI3_CLK_ROOT = 131,
  149. PDM_CLK_ROOT = 132,
  150. VPU_VC8000E_CLK_ROOT = 133,
  151. SAI7_CLK_ROOT = 134,
  152. CLK_ROOT_MAX,
  153. };
  154. #elif defined(CONFIG_IMX8MN)
  155. enum clk_root_index {
  156. ARM_A53_CLK_ROOT = 0,
  157. ARM_M7_CLK_ROOT = 1,
  158. GPU_CORE_CLK_ROOT = 3,
  159. GPU_SHADER_CLK_ROOT = 4,
  160. MAIN_AXI_CLK_ROOT = 16,
  161. ENET_AXI_CLK_ROOT = 17,
  162. NAND_USDHC_BUS_CLK_ROOT = 18,
  163. DISPLAY_AXI_CLK_ROOT = 20,
  164. DISPLAY_APB_CLK_ROOT = 21,
  165. USB_BUS_CLK_ROOT = 23,
  166. GPU_AXI_CLK_ROOT = 24,
  167. GPU_AHB_CLK_ROOT = 25,
  168. NOC_CLK_ROOT = 26,
  169. AHB_CLK_ROOT = 32,
  170. IPG_CLK_ROOT = 33,
  171. AUDIO_AHB_CLK_ROOT = 34,
  172. DRAM_SEL_CFG = 48,
  173. CORE_SEL_CFG = 49,
  174. DRAM_ALT_CLK_ROOT = 64,
  175. DRAM_APB_CLK_ROOT = 65,
  176. DISPLAY_PIXEL_CLK_ROOT = 74,
  177. SAI2_CLK_ROOT = 76,
  178. SAI3_CLK_ROOT = 77,
  179. SAI5_CLK_ROOT = 79,
  180. SAI6_CLK_ROOT = 80,
  181. SPDIF1_CLK_ROOT = 81,
  182. ENET_REF_CLK_ROOT = 83,
  183. ENET_TIMER_CLK_ROOT = 84,
  184. ENET_PHY_REF_CLK_ROOT = 85,
  185. NAND_CLK_ROOT = 86,
  186. QSPI_CLK_ROOT = 87,
  187. USDHC1_CLK_ROOT = 88,
  188. USDHC2_CLK_ROOT = 89,
  189. I2C1_CLK_ROOT = 90,
  190. I2C2_CLK_ROOT = 91,
  191. I2C3_CLK_ROOT = 92,
  192. I2C4_CLK_ROOT = 93,
  193. UART1_CLK_ROOT = 94,
  194. UART2_CLK_ROOT = 95,
  195. UART3_CLK_ROOT = 96,
  196. UART4_CLK_ROOT = 97,
  197. USB_CORE_REF_CLK_ROOT = 98,
  198. USB_PHY_REF_CLK_ROOT = 99,
  199. GIC_CLK_ROOT = 100,
  200. ECSPI1_CLK_ROOT = 101,
  201. ECSPI2_CLK_ROOT = 102,
  202. PWM1_CLK_ROOT = 103,
  203. PWM2_CLK_ROOT = 104,
  204. PWM3_CLK_ROOT = 105,
  205. PWM4_CLK_ROOT = 106,
  206. GPT1_CLK_ROOT = 107,
  207. GPT2_CLK_ROOT = 108,
  208. GPT3_CLK_ROOT = 109,
  209. GPT4_CLK_ROOT = 110,
  210. GPT5_CLK_ROOT = 111,
  211. GPT6_CLK_ROOT = 112,
  212. TRACE_CLK_ROOT = 113,
  213. WDOG_CLK_ROOT = 114,
  214. WRCLK_CLK_ROOT = 115,
  215. IPP_DO_CLKO1 = 116,
  216. IPP_DO_CLKO2 = 117,
  217. MIPI_DSI_CORE_CLK_ROOT = 118,
  218. DISPLAY_DSI_PHY_REF_CLK_ROOT = 119,
  219. MIPI_DSI_DBI_CLK_ROOT = 120,
  220. USDHC3_CLK_ROOT = 121,
  221. DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122,
  222. MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
  223. MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
  224. MIPI_CSI2_ESC_CLK_ROOT = 127,
  225. ECSPI3_CLK_ROOT = 131,
  226. PDM_CLK_ROOT = 132,
  227. SAI7_CLK_ROOT = 134,
  228. CLK_ROOT_MAX,
  229. };
  230. #else
  231. enum clk_root_index {
  232. ARM_A53_CLK_ROOT = 0,
  233. ARM_M4_CLK_ROOT = 1,
  234. VPU_A53_CLK_ROOT = 2,
  235. GPU3D_CLK_ROOT = 3,
  236. GPU2D_CLK_ROOT = 4,
  237. MAIN_AXI_CLK_ROOT = 16,
  238. ENET_AXI_CLK_ROOT = 17,
  239. NAND_USDHC_BUS_CLK_ROOT = 18,
  240. VPU_BUS_CLK_ROOT = 19,
  241. DISPLAY_AXI_CLK_ROOT = 20,
  242. DISPLAY_APB_CLK_ROOT = 21,
  243. DISPLAY_RTRM_CLK_ROOT = 22,
  244. USB_BUS_CLK_ROOT = 23,
  245. GPU_AXI_CLK_ROOT = 24,
  246. GPU_AHB_CLK_ROOT = 25,
  247. NOC_CLK_ROOT = 26,
  248. NOC_APB_CLK_ROOT = 27,
  249. AHB_CLK_ROOT = 32,
  250. IPG_CLK_ROOT = 33,
  251. AUDIO_AHB_CLK_ROOT = 34,
  252. MIPI_DSI_ESC_RX_CLK_ROOT = 36,
  253. DRAM_SEL_CFG = 48,
  254. CORE_SEL_CFG = 49,
  255. DRAM_ALT_CLK_ROOT = 64,
  256. DRAM_APB_CLK_ROOT = 65,
  257. VPU_G1_CLK_ROOT = 66,
  258. VPU_G2_CLK_ROOT = 67,
  259. DISPLAY_DTRC_CLK_ROOT = 68,
  260. DISPLAY_DC8000_CLK_ROOT = 69,
  261. PCIE_CTRL_CLK_ROOT = 70,
  262. PCIE_PHY_CLK_ROOT = 71,
  263. PCIE_AUX_CLK_ROOT = 72,
  264. DC_PIXEL_CLK_ROOT = 73,
  265. LCDIF_PIXEL_CLK_ROOT = 74,
  266. SAI1_CLK_ROOT = 75,
  267. SAI2_CLK_ROOT = 76,
  268. SAI3_CLK_ROOT = 77,
  269. SAI4_CLK_ROOT = 78,
  270. SAI5_CLK_ROOT = 79,
  271. SAI6_CLK_ROOT = 80,
  272. SPDIF1_CLK_ROOT = 81,
  273. SPDIF2_CLK_ROOT = 82,
  274. ENET_REF_CLK_ROOT = 83,
  275. ENET_TIMER_CLK_ROOT = 84,
  276. ENET_PHY_REF_CLK_ROOT = 85,
  277. NAND_CLK_ROOT = 86,
  278. QSPI_CLK_ROOT = 87,
  279. USDHC1_CLK_ROOT = 88,
  280. USDHC2_CLK_ROOT = 89,
  281. I2C1_CLK_ROOT = 90,
  282. I2C2_CLK_ROOT = 91,
  283. I2C3_CLK_ROOT = 92,
  284. I2C4_CLK_ROOT = 93,
  285. UART1_CLK_ROOT = 94,
  286. UART2_CLK_ROOT = 95,
  287. UART3_CLK_ROOT = 96,
  288. UART4_CLK_ROOT = 97,
  289. USB_CORE_REF_CLK_ROOT = 98,
  290. USB_PHY_REF_CLK_ROOT = 99,
  291. GIC_CLK_ROOT = 100,
  292. ECSPI1_CLK_ROOT = 101,
  293. ECSPI2_CLK_ROOT = 102,
  294. PWM1_CLK_ROOT = 103,
  295. PWM2_CLK_ROOT = 104,
  296. PWM3_CLK_ROOT = 105,
  297. PWM4_CLK_ROOT = 106,
  298. GPT1_CLK_ROOT = 107,
  299. GPT2_CLK_ROOT = 108,
  300. GPT3_CLK_ROOT = 109,
  301. GPT4_CLK_ROOT = 110,
  302. GPT5_CLK_ROOT = 111,
  303. GPT6_CLK_ROOT = 112,
  304. TRACE_CLK_ROOT = 113,
  305. WDOG_CLK_ROOT = 114,
  306. WRCLK_CLK_ROOT = 115,
  307. IPP_DO_CLKO1 = 116,
  308. IPP_DO_CLKO2 = 117,
  309. MIPI_DSI_CORE_CLK_ROOT = 118,
  310. MIPI_DSI_PHY_REF_CLK_ROOT = 119,
  311. MIPI_DSI_DBI_CLK_ROOT = 120,
  312. USDHC3_CLK_ROOT = 121,
  313. MIPI_CSI1_CORE_CLK_ROOT = 122,
  314. MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
  315. MIPI_CSI1_ESC_CLK_ROOT = 124,
  316. MIPI_CSI2_CORE_CLK_ROOT = 125,
  317. MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
  318. MIPI_CSI2_ESC_CLK_ROOT = 127,
  319. PCIE2_CTRL_CLK_ROOT = 128,
  320. PCIE2_PHY_CLK_ROOT = 129,
  321. PCIE2_AUX_CLK_ROOT = 130,
  322. ECSPI3_CLK_ROOT = 131,
  323. PDM_CLK_ROOT = 132,
  324. VPU_H1_CLK_ROOT = 133,
  325. CLK_ROOT_MAX,
  326. };
  327. #endif
  328. enum clk_root_src {
  329. OSC_24M_CLK,
  330. ARM_PLL_CLK,
  331. DRAM_PLL1_CLK,
  332. VIDEO_PLL2_CLK,
  333. VPU_PLL_CLK,
  334. GPU_PLL_CLK,
  335. SYSTEM_PLL1_800M_CLK,
  336. SYSTEM_PLL1_400M_CLK,
  337. SYSTEM_PLL1_266M_CLK,
  338. SYSTEM_PLL1_200M_CLK,
  339. SYSTEM_PLL1_160M_CLK,
  340. SYSTEM_PLL1_133M_CLK,
  341. SYSTEM_PLL1_100M_CLK,
  342. SYSTEM_PLL1_80M_CLK,
  343. SYSTEM_PLL1_40M_CLK,
  344. SYSTEM_PLL2_1000M_CLK,
  345. SYSTEM_PLL2_500M_CLK,
  346. SYSTEM_PLL2_333M_CLK,
  347. SYSTEM_PLL2_250M_CLK,
  348. SYSTEM_PLL2_200M_CLK,
  349. SYSTEM_PLL2_166M_CLK,
  350. SYSTEM_PLL2_125M_CLK,
  351. SYSTEM_PLL2_100M_CLK,
  352. SYSTEM_PLL2_50M_CLK,
  353. SYSTEM_PLL3_CLK,
  354. AUDIO_PLL1_CLK,
  355. AUDIO_PLL2_CLK,
  356. VIDEO_PLL_CLK,
  357. OSC_32K_CLK,
  358. EXT_CLK_1,
  359. EXT_CLK_2,
  360. EXT_CLK_3,
  361. EXT_CLK_4,
  362. OSC_HDMI_CLK,
  363. ARM_A53_ALT_CLK,
  364. };
  365. enum clk_ccgr_index {
  366. CCGR_DVFS = 0,
  367. CCGR_ANAMIX = 1,
  368. CCGR_CPU = 2,
  369. CCGR_CSU = 3,
  370. CCGR_DEBUG = 4,
  371. CCGR_DDR1 = 5,
  372. CCGR_ECSPI1 = 7,
  373. CCGR_ECSPI2 = 8,
  374. CCGR_ECSPI3 = 9,
  375. CCGR_ENET1 = 10,
  376. CCGR_GPIO1 = 11,
  377. CCGR_GPIO2 = 12,
  378. CCGR_GPIO3 = 13,
  379. CCGR_GPIO4 = 14,
  380. CCGR_GPIO5 = 15,
  381. CCGR_GPT1 = 16,
  382. CCGR_GPT2 = 17,
  383. CCGR_GPT3 = 18,
  384. CCGR_GPT4 = 19,
  385. CCGR_AAM_8MP = 20,
  386. CCGR_GPT5 = 20,
  387. CCGR_GPT6 = 21,
  388. CCGR_HS = 22,
  389. CCGR_I2C1 = 23,
  390. CCGR_I2C2 = 24,
  391. CCGR_I2C3 = 25,
  392. CCGR_I2C4 = 26,
  393. CCGR_IOMUX = 27,
  394. CCGR_IOMUX1 = 28,
  395. CCGR_IOMUX2 = 29,
  396. CCGR_IOMUX3 = 30,
  397. CCGR_IOMUX4 = 31,
  398. CCGR_SNVSMIX_IPG_CLK = 32,
  399. CCGR_MU = 33,
  400. CCGR_OCOTP = 34,
  401. CCGR_OCRAM = 35,
  402. CCGR_OCRAM_S = 36,
  403. CCGR_PCIE = 37,
  404. CCGR_PERFMON1 = 38,
  405. CCGR_PERFMON2 = 39,
  406. CCGR_PWM1 = 40,
  407. CCGR_PWM2 = 41,
  408. CCGR_PWM3 = 42,
  409. CCGR_PWM4 = 43,
  410. CCGR_QOS = 44,
  411. CCGR_QOS_DISPMIX = 45,
  412. CCGR_QOS_ETHENET = 46,
  413. CCGR_QSPI = 47,
  414. CCGR_RAWNAND = 48,
  415. CCGR_RDC = 49,
  416. CCGR_ROM = 50,
  417. CCGR_I2C5_8MP = 51,
  418. CCGR_SAI1 = 51,
  419. CCGR_I2C6_8MP = 52,
  420. CCGR_SAI2 = 52,
  421. CCGR_SAI3 = 53,
  422. CCGR_SAI4 = 54,
  423. CCGR_SAI5 = 55,
  424. CCGR_SAI6 = 56,
  425. CCGR_SCTR = 57,
  426. CCGR_SDMA1 = 58,
  427. CCGR_SDMA2 = 59,
  428. CCGR_SEC_DEBUG = 60,
  429. CCGR_SEMA1 = 61,
  430. CCGR_SEMA2 = 62,
  431. CCGR_IRQ_STEER_8MP = 63,
  432. CCGR_SIM_DISPLAY = 63,
  433. CCGR_SIM_ENET = 64,
  434. CCGR_SIM_M = 65,
  435. CCGR_SIM_MAIN = 66,
  436. CCGR_SIM_S = 67,
  437. CCGR_SIM_WAKEUP = 68,
  438. CCGR_GPU2D_8MP = 69,
  439. CCGR_SIM_HSIO = 69,
  440. CCGR_GPU3D_8MP = 70,
  441. CCGR_SIM_VPU = 70,
  442. CCGR_SNVS = 71,
  443. CCGR_TRACE = 72,
  444. CCGR_UART1 = 73,
  445. CCGR_UART2 = 74,
  446. CCGR_UART3 = 75,
  447. CCGR_UART4 = 76,
  448. CCGR_USB_MSCALE_PL301 = 77,
  449. CCGR_USB_PHY_8MP = 79,
  450. CCGR_GPU3D = 79,
  451. CCGR_USDHC1 = 81,
  452. CCGR_USDHC2 = 82,
  453. CCGR_WDOG1 = 83,
  454. CCGR_WDOG2 = 84,
  455. CCGR_WDOG3 = 85,
  456. CCGR_VPUG1 = 86,
  457. CCGR_GPU_BUS = 87,
  458. CCGR_VPUH1 = 89,
  459. CCGR_VPUG2 = 90,
  460. CCGR_PDM = 91,
  461. CCGR_GIC = 92,
  462. CCGR_DISPMIX = 93,
  463. CCGR_USDHC3 = 94,
  464. CCGR_SDMA3 = 95,
  465. CCGR_XTAL = 96,
  466. CCGR_PLL = 97,
  467. CCGR_TEMP_SENSOR = 98,
  468. CCGR_VPUMIX_BUS = 99,
  469. CCGR_SAI7 = 101,
  470. CCGR_GPU2D = 102,
  471. CCGR_MAX
  472. };
  473. enum clk_src_index {
  474. CLK_SRC_CKIL_SYNC_REQ = 0,
  475. CLK_SRC_ARM_PLL_EN = 1,
  476. CLK_SRC_GPU_PLL_EN = 2,
  477. CLK_SRC_VPU_PLL_EN = 3,
  478. CLK_SRC_DRAM_PLL_EN = 4,
  479. CLK_SRC_SYSTEM_PLL1_EN = 5,
  480. CLK_SRC_SYSTEM_PLL2_EN = 6,
  481. CLK_SRC_SYSTEM_PLL3_EN = 7,
  482. CLK_SRC_AUDIO_PLL1_EN = 8,
  483. CLK_SRC_AUDIO_PLL2_EN = 9,
  484. CLK_SRC_VIDEO_PLL1_EN = 10,
  485. CLK_SRC_RESERVED = 11,
  486. CLK_SRC_ARM_PLL = 12,
  487. CLK_SRC_GPU_PLL = 13,
  488. CLK_SRC_VPU_PLL = 14,
  489. CLK_SRC_DRAM_PLL = 15,
  490. CLK_SRC_SYSTEM_PLL1_800M = 16,
  491. CLK_SRC_SYSTEM_PLL1_400M = 17,
  492. CLK_SRC_SYSTEM_PLL1_266M = 18,
  493. CLK_SRC_SYSTEM_PLL1_200M = 19,
  494. CLK_SRC_SYSTEM_PLL1_160M = 20,
  495. CLK_SRC_SYSTEM_PLL1_133M = 21,
  496. CLK_SRC_SYSTEM_PLL1_100M = 22,
  497. CLK_SRC_SYSTEM_PLL1_80M = 23,
  498. CLK_SRC_SYSTEM_PLL1_40M = 24,
  499. CLK_SRC_SYSTEM_PLL2_1000M = 25,
  500. CLK_SRC_SYSTEM_PLL2_500M = 26,
  501. CLK_SRC_SYSTEM_PLL2_333M = 27,
  502. CLK_SRC_SYSTEM_PLL2_250M = 28,
  503. CLK_SRC_SYSTEM_PLL2_200M = 29,
  504. CLK_SRC_SYSTEM_PLL2_166M = 30,
  505. CLK_SRC_SYSTEM_PLL2_125M = 31,
  506. CLK_SRC_SYSTEM_PLL2_100M = 32,
  507. CLK_SRC_SYSTEM_PLL2_50M = 33,
  508. CLK_SRC_SYSTEM_PLL3 = 34,
  509. CLK_SRC_AUDIO_PLL1 = 35,
  510. CLK_SRC_AUDIO_PLL2 = 36,
  511. CLK_SRC_VIDEO_PLL1 = 37,
  512. };
  513. #define INTPLL_LOCK_MASK BIT(31)
  514. #define INTPLL_LOCK_SEL_MASK BIT(29)
  515. #define INTPLL_EXT_BYPASS_MASK BIT(28)
  516. #define INTPLL_DIV20_CLKE_MASK BIT(27)
  517. #define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
  518. #define INTPLL_DIV10_CLKE_MASK BIT(25)
  519. #define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
  520. #define INTPLL_DIV8_CLKE_MASK BIT(23)
  521. #define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
  522. #define INTPLL_DIV6_CLKE_MASK BIT(21)
  523. #define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
  524. #define INTPLL_DIV5_CLKE_MASK BIT(19)
  525. #define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
  526. #define INTPLL_DIV4_CLKE_MASK BIT(17)
  527. #define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
  528. #define INTPLL_DIV3_CLKE_MASK BIT(15)
  529. #define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
  530. #define INTPLL_DIV2_CLKE_MASK BIT(13)
  531. #define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
  532. #define INTPLL_CLKE_MASK BIT(11)
  533. #define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
  534. #define INTPLL_RST_MASK BIT(9)
  535. #define INTPLL_RST_OVERRIDE_MASK BIT(8)
  536. #define INTPLL_BYPASS_MASK BIT(4)
  537. #define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
  538. #define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
  539. #define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
  540. #define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
  541. #define INTPLL_MAIN_DIV_SHIFT 12
  542. #define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
  543. #define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
  544. #define INTPLL_PRE_DIV_SHIFT 4
  545. #define INTPLL_POST_DIV_MASK GENMASK(2, 0)
  546. #define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
  547. #define INTPLL_POST_DIV_SHIFT 0
  548. #define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
  549. #define INTPLL_LOCK_CON_DLY_SHIFT 4
  550. #define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
  551. #define INTPLL_LOCK_CON_OUT_SHIFT 2
  552. #define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
  553. #define INTPLL_LOCK_CON_IN_SHIFT 0
  554. #define INTPLL_LRD_EN_MASK BIT(21)
  555. #define INTPLL_FOUT_MASK BIT(20)
  556. #define INTPLL_AFC_SEL_MASK BIT(19)
  557. #define INTPLL_PBIAS_CTRL_MASK BIT(18)
  558. #define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
  559. #define INTPLL_AFCINIT_SEL_MASK BIT(16)
  560. #define INTPLL_FSEL_MASK BIT(14)
  561. #define INTPLL_FEED_EN_MASK BIT(13)
  562. #define INTPLL_EXTAFC_MASK GENMASK(7, 3)
  563. #define INTPLL_AFC_EN_MASK BIT(2)
  564. #define INTPLL_ICP_MASK GENMASK(1, 0)
  565. #endif