pinmux.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Linaro.
  4. * Peter Griffin <peter.griffin@linaro.org>
  5. */
  6. #include <common.h>
  7. #include <fdtdec.h>
  8. #include <log.h>
  9. #include <asm/gpio.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/pinmux.h>
  12. #include <linux/bitops.h>
  13. struct hi6220_pinmux0_regs *pmx0 =
  14. (struct hi6220_pinmux0_regs *)HI6220_PINMUX0_BASE;
  15. struct hi6220_pinmux1_regs *pmx1 =
  16. (struct hi6220_pinmux1_regs *)HI6220_PINMUX1_BASE;
  17. static void hi6220_uart_config(int peripheral)
  18. {
  19. switch (peripheral) {
  20. case PERIPH_ID_UART0:
  21. writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */
  22. writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */
  23. writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */
  24. writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */
  25. break;
  26. case PERIPH_ID_UART1:
  27. writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */
  28. writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */
  29. writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */
  30. writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */
  31. writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/
  32. writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */
  33. writel(DRIVE1_02MA, &pmx1->iocfg[52]); /* UART1_RTS_N */
  34. writel(DRIVE1_02MA, &pmx1->iocfg[54]); /* UART1_TXD */
  35. break;
  36. case PERIPH_ID_UART2:
  37. writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */
  38. writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */
  39. writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */
  40. writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */
  41. writel(DRIVE1_02MA, &pmx1->iocfg[55]); /* UART2_CTS_N */
  42. writel(DRIVE1_02MA, &pmx1->iocfg[56]); /* UART2_RTS_N */
  43. writel(DRIVE1_02MA, &pmx1->iocfg[57]); /* UART2_RXD */
  44. writel(DRIVE1_02MA, &pmx1->iocfg[58]); /* UART2_TXD */
  45. break;
  46. case PERIPH_ID_UART3:
  47. writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */
  48. writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */
  49. writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */
  50. writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */
  51. /* UART3_TXD */
  52. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[100]);
  53. /* UART3_RTS_N */
  54. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[101]);
  55. /* UART3_RXD */
  56. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[102]);
  57. /* UART3_TXD */
  58. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[103]);
  59. break;
  60. case PERIPH_ID_UART4:
  61. writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */
  62. writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */
  63. writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */
  64. writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */
  65. /* UART4_CTS_N */
  66. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[120]);
  67. /* UART4_RTS_N */
  68. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[121]);
  69. /* UART4_RXD */
  70. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[122]);
  71. /* UART4_TXD */
  72. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[123]);
  73. break;
  74. case PERIPH_ID_UART5:
  75. writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */
  76. writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */
  77. /* UART5_RXD */
  78. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[118]);
  79. /* UART5_TXD */
  80. writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[119]);
  81. break;
  82. default:
  83. debug("%s: invalid peripheral %d", __func__, peripheral);
  84. return;
  85. }
  86. }
  87. static int hi6220_mmc_config(int peripheral)
  88. {
  89. u32 tmp;
  90. switch (peripheral) {
  91. case PERIPH_ID_SDMMC0:
  92. /* eMMC pinmux config */
  93. writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */
  94. writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */
  95. writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */
  96. writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */
  97. writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */
  98. writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */
  99. writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */
  100. writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */
  101. writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */
  102. writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */
  103. /*eMMC configure up/down/drive */
  104. writel(DRIVE1_08MA, &pmx1->iocfg[65]); /* EMMC_CLK */
  105. tmp = DRIVE1_04MA | PULL_UP;
  106. writel(tmp, &pmx1->iocfg[65]); /* EMMC_CMD */
  107. writel(tmp, &pmx1->iocfg[66]); /* EMMC_DATA0 */
  108. writel(tmp, &pmx1->iocfg[67]); /* EMMC_DATA1 */
  109. writel(tmp, &pmx1->iocfg[68]); /* EMMC_DATA2 */
  110. writel(tmp, &pmx1->iocfg[69]); /* EMMC_DATA3 */
  111. writel(tmp, &pmx1->iocfg[70]); /* EMMC_DATA4 */
  112. writel(tmp, &pmx1->iocfg[71]); /* EMMC_DATA5 */
  113. writel(tmp, &pmx1->iocfg[72]); /* EMMC_DATA6 */
  114. writel(tmp, &pmx1->iocfg[73]); /* EMMC_DATA7 */
  115. writel(DRIVE1_04MA, &pmx1->iocfg[73]); /* EMMC_RST_N */
  116. break;
  117. case PERIPH_ID_SDMMC1:
  118. writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */
  119. writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */
  120. writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */
  121. writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */
  122. writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */
  123. writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */
  124. writel(DRIVE1_10MA | BIT(2), &pmx1->iocfg[3]); /*SD_CLK*/
  125. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[4]); /*SD_CMD*/
  126. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[5]); /*SD_DATA0*/
  127. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[6]); /*SD_DATA1*/
  128. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[7]); /*SD_DATA2*/
  129. writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[8]); /*SD_DATA3*/
  130. break;
  131. default:
  132. debug("%s: invalid peripheral %d", __func__, peripheral);
  133. return -1;
  134. }
  135. return 0;
  136. }
  137. int hi6220_pinmux_config(int peripheral)
  138. {
  139. switch (peripheral) {
  140. case PERIPH_ID_UART0:
  141. case PERIPH_ID_UART1:
  142. case PERIPH_ID_UART2:
  143. case PERIPH_ID_UART3:
  144. hi6220_uart_config(peripheral);
  145. break;
  146. case PERIPH_ID_SDMMC0:
  147. case PERIPH_ID_SDMMC1:
  148. return hi6220_mmc_config(peripheral);
  149. default:
  150. debug("%s: invalid peripheral %d", __func__, peripheral);
  151. return -1;
  152. }
  153. return 0;
  154. }