fsl_lsch3_serdes.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016-2018 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <linux/bitops.h>
  11. #include <linux/delay.h>
  12. #include <linux/errno.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #include <asm/arch/soc.h>
  15. #include <fsl-mc/ldpaa_wriop.h>
  16. #ifdef CONFIG_SYS_FSL_SRDS_1
  17. static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  18. #endif
  19. #ifdef CONFIG_SYS_FSL_SRDS_2
  20. static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  21. #endif
  22. #ifdef CONFIG_SYS_NXP_SRDS_3
  23. static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  24. #endif
  25. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  26. #ifdef CONFIG_ARCH_LX2160A
  27. int xfi_dpmac[XFI14 + 1];
  28. int sgmii_dpmac[SGMII18 + 1];
  29. int a25gaui_dpmac[_25GE10 + 1];
  30. int xlaui_dpmac[_40GE2 + 1];
  31. int caui2_dpmac[_50GE2 + 1];
  32. int caui4_dpmac[_100GE2 + 1];
  33. #else
  34. int xfi_dpmac[XFI8 + 1];
  35. int sgmii_dpmac[SGMII16 + 1];
  36. #endif
  37. #endif
  38. __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  39. {
  40. return;
  41. }
  42. /*
  43. *The return value of this func is the serdes protocol used.
  44. *Typically this function is called number of times depending
  45. *upon the number of serdes blocks in the Silicon.
  46. *Zero is used to denote that no serdes was enabled,
  47. *this is the case when golden RCW was used where DPAA2 bring was
  48. *intentionally removed to achieve boot to prompt
  49. */
  50. __weak int serdes_get_number(int serdes, int cfg)
  51. {
  52. return cfg;
  53. }
  54. int is_serdes_configured(enum srds_prtcl device)
  55. {
  56. int ret = 0;
  57. #ifdef CONFIG_SYS_FSL_SRDS_1
  58. if (!serdes1_prtcl_map[NONE])
  59. fsl_serdes_init();
  60. ret |= serdes1_prtcl_map[device];
  61. #endif
  62. #ifdef CONFIG_SYS_FSL_SRDS_2
  63. if (!serdes2_prtcl_map[NONE])
  64. fsl_serdes_init();
  65. ret |= serdes2_prtcl_map[device];
  66. #endif
  67. #ifdef CONFIG_SYS_NXP_SRDS_3
  68. if (!serdes3_prtcl_map[NONE])
  69. fsl_serdes_init();
  70. ret |= serdes3_prtcl_map[device];
  71. #endif
  72. return !!ret;
  73. }
  74. int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  75. {
  76. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  77. u32 cfg = 0;
  78. int i;
  79. switch (sd) {
  80. #ifdef CONFIG_SYS_FSL_SRDS_1
  81. case FSL_SRDS_1:
  82. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  83. cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  84. cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  85. break;
  86. #endif
  87. #ifdef CONFIG_SYS_FSL_SRDS_2
  88. case FSL_SRDS_2:
  89. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  90. cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
  91. cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
  92. break;
  93. #endif
  94. #ifdef CONFIG_SYS_NXP_SRDS_3
  95. case NXP_SRDS_3:
  96. cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
  97. cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
  98. cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
  99. break;
  100. #endif
  101. default:
  102. printf("invalid SerDes%d\n", sd);
  103. break;
  104. }
  105. cfg = serdes_get_number(sd, cfg);
  106. /* Is serdes enabled at all? */
  107. if (cfg == 0)
  108. return -ENODEV;
  109. for (i = 0; i < SRDS_MAX_LANES; i++) {
  110. if (serdes_get_prtcl(sd, cfg, i) == device)
  111. return i;
  112. }
  113. return -ENODEV;
  114. }
  115. void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
  116. u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
  117. {
  118. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  119. u32 cfg;
  120. int lane;
  121. if (serdes_prtcl_map[NONE])
  122. return;
  123. memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
  124. cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  125. cfg >>= sd_prctl_shift;
  126. cfg = serdes_get_number(sd, cfg);
  127. printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  128. if (!is_serdes_prtcl_valid(sd, cfg))
  129. printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  130. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  131. enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  132. if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
  133. debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
  134. else {
  135. serdes_prtcl_map[lane_prtcl] = 1;
  136. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  137. #ifdef CONFIG_ARCH_LX2160A
  138. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
  139. wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
  140. (int)lane_prtcl);
  141. if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
  142. wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
  143. (int)lane_prtcl);
  144. if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
  145. wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
  146. (int)lane_prtcl);
  147. if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
  148. wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
  149. (int)lane_prtcl);
  150. if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
  151. wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
  152. (int)lane_prtcl);
  153. if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
  154. wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
  155. (int)lane_prtcl);
  156. #else
  157. switch (lane_prtcl) {
  158. case QSGMII_A:
  159. case QSGMII_B:
  160. case QSGMII_C:
  161. case QSGMII_D:
  162. wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
  163. break;
  164. default:
  165. if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
  166. wriop_init_dpmac(sd,
  167. xfi_dpmac[lane_prtcl],
  168. (int)lane_prtcl);
  169. if (lane_prtcl >= SGMII1 &&
  170. lane_prtcl <= SGMII16)
  171. wriop_init_dpmac(sd, sgmii_dpmac[
  172. lane_prtcl],
  173. (int)lane_prtcl);
  174. break;
  175. }
  176. #endif
  177. #endif
  178. }
  179. }
  180. /* Set the first element to indicate serdes has been initialized */
  181. serdes_prtcl_map[NONE] = 1;
  182. }
  183. __weak int get_serdes_volt(void)
  184. {
  185. return -1;
  186. }
  187. __weak int set_serdes_volt(int svdd)
  188. {
  189. return -1;
  190. }
  191. #define LNAGCR0_RT_RSTB 0x00600000
  192. #define RSTCTL_RESET_MASK 0x000000E0
  193. #define RSTCTL_RSTREQ 0x80000000
  194. #define RSTCTL_RST_DONE 0x40000000
  195. #define RSTCTL_RSTERR 0x20000000
  196. #define RSTCTL_SDEN 0x00000020
  197. #define RSTCTL_SDRST_B 0x00000040
  198. #define RSTCTL_PLLRST_B 0x00000080
  199. #define TCALCR_CALRST_B 0x08000000
  200. struct serdes_prctl_info {
  201. u32 id;
  202. u32 mask;
  203. u32 shift;
  204. };
  205. struct serdes_prctl_info srds_prctl_info[] = {
  206. #ifdef CONFIG_SYS_FSL_SRDS_1
  207. {.id = 1,
  208. .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  209. .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
  210. },
  211. #endif
  212. #ifdef CONFIG_SYS_FSL_SRDS_2
  213. {.id = 2,
  214. .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  215. .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
  216. },
  217. #endif
  218. #ifdef CONFIG_SYS_NXP_SRDS_3
  219. {.id = 3,
  220. .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  221. .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
  222. },
  223. #endif
  224. {} /* NULL ENTRY */
  225. };
  226. static int get_serdes_prctl_info_idx(u32 serdes_id)
  227. {
  228. int pos = 0;
  229. struct serdes_prctl_info *srds_info;
  230. /* loop until NULL ENTRY defined by .id=0 */
  231. for (srds_info = srds_prctl_info; srds_info->id != 0;
  232. srds_info++, pos++) {
  233. if (srds_info->id == serdes_id)
  234. return pos;
  235. }
  236. return -1;
  237. }
  238. static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
  239. struct ccsr_serdes __iomem *serdes_base,
  240. bool cmplt)
  241. {
  242. int i, pos;
  243. u32 cfg_tmp;
  244. pos = get_serdes_prctl_info_idx(serdes_id);
  245. if (pos == -1) {
  246. printf("invalid serdes_id %d\n", serdes_id);
  247. return;
  248. }
  249. cfg_tmp = cfg & srds_prctl_info[pos].mask;
  250. cfg_tmp >>= srds_prctl_info[pos].shift;
  251. for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
  252. if (cmplt)
  253. setbits_le32(&serdes_base->lane[i].gcr0,
  254. LNAGCR0_RT_RSTB);
  255. else
  256. clrbits_le32(&serdes_base->lane[i].gcr0,
  257. LNAGCR0_RT_RSTB);
  258. }
  259. }
  260. static void do_pll_reset(u32 cfg,
  261. struct ccsr_serdes __iomem *serdes_base)
  262. {
  263. int i;
  264. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  265. clrbits_le32(&serdes_base->bank[i].rstctl,
  266. RSTCTL_RESET_MASK);
  267. udelay(1);
  268. setbits_le32(&serdes_base->bank[i].rstctl,
  269. RSTCTL_RSTREQ);
  270. }
  271. udelay(1);
  272. }
  273. static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
  274. {
  275. clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  276. clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  277. }
  278. static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
  279. struct ccsr_serdes __iomem *serdes_base)
  280. {
  281. if (!(cfg == 0x3 && i == 1)) {
  282. udelay(1);
  283. setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  284. setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
  285. }
  286. udelay(1);
  287. }
  288. static void do_pll_reset_done(u32 cfg,
  289. struct ccsr_serdes __iomem *serdes_base)
  290. {
  291. int i;
  292. u32 reg = 0;
  293. for (i = 0; i < 2; i++) {
  294. reg = in_le32(&serdes_base->bank[i].pllcr0);
  295. if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
  296. setbits_le32(&serdes_base->bank[i].rstctl,
  297. RSTCTL_RST_DONE);
  298. }
  299. }
  300. }
  301. static void do_serdes_enable(u32 cfg,
  302. struct ccsr_serdes __iomem *serdes_base)
  303. {
  304. int i;
  305. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  306. setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
  307. udelay(1);
  308. setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
  309. udelay(1);
  310. /* Take the Rx/Tx calibration out of reset */
  311. do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
  312. }
  313. }
  314. static void do_pll_lock(u32 cfg,
  315. struct ccsr_serdes __iomem *serdes_base)
  316. {
  317. int i;
  318. u32 reg = 0;
  319. for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
  320. /* if the PLL is not locked, set RST_ERR */
  321. reg = in_le32(&serdes_base->bank[i].pllcr0);
  322. if (!((reg >> 23) & 0x1)) {
  323. setbits_le32(&serdes_base->bank[i].rstctl,
  324. RSTCTL_RSTERR);
  325. } else {
  326. udelay(1);
  327. setbits_le32(&serdes_base->bank[i].rstctl,
  328. RSTCTL_SDRST_B);
  329. udelay(1);
  330. }
  331. }
  332. }
  333. int setup_serdes_volt(u32 svdd)
  334. {
  335. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  336. struct ccsr_serdes __iomem *serdes1_base =
  337. (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
  338. u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  339. #ifdef CONFIG_SYS_FSL_SRDS_2
  340. struct ccsr_serdes __iomem *serdes2_base =
  341. (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
  342. u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  343. #endif
  344. #ifdef CONFIG_SYS_NXP_SRDS_3
  345. struct ccsr_serdes __iomem *serdes3_base =
  346. (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
  347. u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
  348. #endif
  349. u32 cfg_tmp;
  350. int svdd_cur, svdd_tar;
  351. int ret = 1;
  352. /* Only support switch SVDD to 900mV */
  353. if (svdd != 900)
  354. return -EINVAL;
  355. /* Scale up to the LTC resolution is 1/4096V */
  356. svdd = (svdd * 4096) / 1000;
  357. svdd_tar = svdd;
  358. svdd_cur = get_serdes_volt();
  359. if (svdd_cur < 0)
  360. return -EINVAL;
  361. debug("%s: current SVDD: %x; target SVDD: %x\n",
  362. __func__, svdd_cur, svdd_tar);
  363. if (svdd_cur == svdd_tar)
  364. return 0;
  365. /* Put the all enabled lanes in reset */
  366. #ifdef CONFIG_SYS_FSL_SRDS_1
  367. do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
  368. #endif
  369. #ifdef CONFIG_SYS_FSL_SRDS_2
  370. do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
  371. #endif
  372. #ifdef CONFIG_SYS_NXP_SRDS_3
  373. do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
  374. #endif
  375. /* Put the all enabled PLL in reset */
  376. #ifdef CONFIG_SYS_FSL_SRDS_1
  377. cfg_tmp = cfg_rcwsrds1 & 0x3;
  378. do_pll_reset(cfg_tmp, serdes1_base);
  379. #endif
  380. #ifdef CONFIG_SYS_FSL_SRDS_2
  381. cfg_tmp = cfg_rcwsrds1 & 0xC;
  382. cfg_tmp >>= 2;
  383. do_pll_reset(cfg_tmp, serdes2_base);
  384. #endif
  385. #ifdef CONFIG_SYS_NXP_SRDS_3
  386. cfg_tmp = cfg_rcwsrds3 & 0x30;
  387. cfg_tmp >>= 4;
  388. do_pll_reset(cfg_tmp, serdes3_base);
  389. #endif
  390. /* Put the Rx/Tx calibration into reset */
  391. #ifdef CONFIG_SYS_FSL_SRDS_1
  392. do_rx_tx_cal_reset(serdes1_base);
  393. #endif
  394. #ifdef CONFIG_SYS_FSL_SRDS_2
  395. do_rx_tx_cal_reset(serdes2_base);
  396. #endif
  397. #ifdef CONFIG_SYS_NXP_SRDS_3
  398. do_rx_tx_cal_reset(serdes3_base);
  399. #endif
  400. ret = set_serdes_volt(svdd);
  401. if (ret < 0) {
  402. printf("could not change SVDD\n");
  403. ret = -1;
  404. }
  405. /* For each PLL that’s not disabled via RCW enable the SERDES */
  406. #ifdef CONFIG_SYS_FSL_SRDS_1
  407. cfg_tmp = cfg_rcwsrds1 & 0x3;
  408. do_serdes_enable(cfg_tmp, serdes1_base);
  409. #endif
  410. #ifdef CONFIG_SYS_FSL_SRDS_2
  411. cfg_tmp = cfg_rcwsrds1 & 0xC;
  412. cfg_tmp >>= 2;
  413. do_serdes_enable(cfg_tmp, serdes2_base);
  414. #endif
  415. #ifdef CONFIG_SYS_NXP_SRDS_3
  416. cfg_tmp = cfg_rcwsrds3 & 0x30;
  417. cfg_tmp >>= 4;
  418. do_serdes_enable(cfg_tmp, serdes3_base);
  419. #endif
  420. /* Wait for at at least 625us, ensure the PLLs being reset are locked */
  421. udelay(800);
  422. #ifdef CONFIG_SYS_FSL_SRDS_1
  423. cfg_tmp = cfg_rcwsrds1 & 0x3;
  424. do_pll_lock(cfg_tmp, serdes1_base);
  425. #endif
  426. #ifdef CONFIG_SYS_FSL_SRDS_2
  427. cfg_tmp = cfg_rcwsrds1 & 0xC;
  428. cfg_tmp >>= 2;
  429. do_pll_lock(cfg_tmp, serdes2_base);
  430. #endif
  431. #ifdef CONFIG_SYS_NXP_SRDS_3
  432. cfg_tmp = cfg_rcwsrds3 & 0x30;
  433. cfg_tmp >>= 4;
  434. do_pll_lock(cfg_tmp, serdes3_base);
  435. #endif
  436. /* Take the all enabled lanes out of reset */
  437. #ifdef CONFIG_SYS_FSL_SRDS_1
  438. do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
  439. #endif
  440. #ifdef CONFIG_SYS_FSL_SRDS_2
  441. do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
  442. #endif
  443. #ifdef CONFIG_SYS_NXP_SRDS_3
  444. do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
  445. #endif
  446. /* For each PLL being reset, and achieved PLL lock set RST_DONE */
  447. #ifdef CONFIG_SYS_FSL_SRDS_1
  448. cfg_tmp = cfg_rcwsrds1 & 0x3;
  449. do_pll_reset_done(cfg_tmp, serdes1_base);
  450. #endif
  451. #ifdef CONFIG_SYS_FSL_SRDS_2
  452. cfg_tmp = cfg_rcwsrds1 & 0xC;
  453. cfg_tmp >>= 2;
  454. do_pll_reset_done(cfg_tmp, serdes2_base);
  455. #endif
  456. #ifdef CONFIG_SYS_NXP_SRDS_3
  457. cfg_tmp = cfg_rcwsrds3 & 0x30;
  458. cfg_tmp >>= 4;
  459. do_pll_reset_done(cfg_tmp, serdes3_base);
  460. #endif
  461. return ret;
  462. }
  463. void fsl_serdes_init(void)
  464. {
  465. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  466. int i , j;
  467. #ifdef CONFIG_ARCH_LX2160A
  468. for (i = XFI1, j = 1; i <= XFI14; i++, j++)
  469. xfi_dpmac[i] = j;
  470. for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
  471. sgmii_dpmac[i] = j;
  472. for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
  473. a25gaui_dpmac[i] = j;
  474. for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
  475. xlaui_dpmac[i] = j;
  476. for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
  477. caui2_dpmac[i] = j;
  478. for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
  479. caui4_dpmac[i] = j;
  480. #else
  481. for (i = XFI1, j = 1; i <= XFI8; i++, j++)
  482. xfi_dpmac[i] = j;
  483. for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
  484. sgmii_dpmac[i] = j;
  485. #endif
  486. #endif
  487. #ifdef CONFIG_SYS_FSL_SRDS_1
  488. serdes_init(FSL_SRDS_1,
  489. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
  490. FSL_CHASSIS3_SRDS1_REGSR,
  491. FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  492. FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
  493. serdes1_prtcl_map);
  494. #endif
  495. #ifdef CONFIG_SYS_FSL_SRDS_2
  496. serdes_init(FSL_SRDS_2,
  497. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
  498. FSL_CHASSIS3_SRDS2_REGSR,
  499. FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  500. FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
  501. serdes2_prtcl_map);
  502. #endif
  503. #ifdef CONFIG_SYS_NXP_SRDS_3
  504. serdes_init(NXP_SRDS_3,
  505. CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
  506. FSL_CHASSIS3_SRDS3_REGSR,
  507. FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  508. FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
  509. serdes3_prtcl_map);
  510. #endif
  511. }
  512. int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
  513. {
  514. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  515. char scfg[16], snum[16];
  516. int cfgr = 0;
  517. u32 cfg;
  518. cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
  519. cfg >>= sd_prctl_shift;
  520. cfg = serdes_get_number(sd, cfg);
  521. #if defined(SRDS_BITS_PER_LANE)
  522. /*
  523. * reverse lanes, lane 0 should be printed first so it must be moved to
  524. * high order bits.
  525. * For example bb58 should read 85bb, lane 0 being protocol 8.
  526. * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
  527. * independent per-lane protocol configuration, at this time LS1028A and
  528. * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
  529. * lanes as a single value.
  530. */
  531. for (int i = 0; i < SRDS_MAX_LANES; i++) {
  532. int tmp;
  533. tmp = cfg >> (i * SRDS_BITS_PER_LANE);
  534. tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
  535. tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
  536. cfgr |= tmp;
  537. }
  538. #endif /* SRDS_BITS_PER_LANE */
  539. snprintf(snum, 16, "serdes%d", sd);
  540. snprintf(scfg, 16, "%x", cfgr);
  541. env_set(snum, scfg);
  542. return 0;
  543. }
  544. int serdes_misc_init(void)
  545. {
  546. #ifdef CONFIG_SYS_FSL_SRDS_1
  547. serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
  548. FSL_CHASSIS3_SRDS1_PRTCL_MASK,
  549. FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
  550. #endif
  551. #ifdef CONFIG_SYS_FSL_SRDS_2
  552. serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
  553. FSL_CHASSIS3_SRDS2_PRTCL_MASK,
  554. FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
  555. #endif
  556. #ifdef CONFIG_SYS_NXP_SRDS_3
  557. serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
  558. FSL_CHASSIS3_SRDS3_PRTCL_MASK,
  559. FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
  560. #endif
  561. return 0;
  562. }