atm.c 27 KB

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  1. #include <common.h>
  2. #include <mpc8xx.h>
  3. #include <commproc.h>
  4. #include "atm.h"
  5. #include <linux/stddef.h>
  6. #define SYNC __asm__("sync")
  7. #define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
  8. #define FALSE 1
  9. #define TRUE 0
  10. #define OK 0
  11. #define ERROR -1
  12. struct atm_connection_t g_conn[NUM_CONNECTIONS] =
  13. {
  14. { NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */
  15. };
  16. struct atm_driver_t g_atm =
  17. {
  18. FALSE, /* loaded */
  19. FALSE, /* started */
  20. NULL, /* csram */
  21. 0, /* csram_size */
  22. NULL, /* am_top */
  23. NULL, /* ap_top */
  24. NULL, /* int_reload_ptr */
  25. NULL, /* int_serv_ptr */
  26. NULL, /* rbd_base_ptr */
  27. NULL, /* tbd_base_ptr */
  28. 0 /* linerate */
  29. };
  30. char csram[1024]; /* more than enough for doing nothing*/
  31. int atmLoad(void);
  32. void atmUnload(void);
  33. int atmMemInit(void);
  34. void atmIntInit(void);
  35. void atmApcInit(void);
  36. void atmAmtInit(void);
  37. void atmCpmInit(void);
  38. void atmUtpInit(void);
  39. /*****************************************************************************
  40. *
  41. * FUNCTION NAME: atmLoad
  42. *
  43. * DESCRIPTION: Basic ATM initialization.
  44. *
  45. * PARAMETERS: none
  46. *
  47. * RETURNS: OK or ERROR
  48. *
  49. ****************************************************************************/
  50. int atmLoad()
  51. {
  52. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  53. volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
  54. volatile iop8xx_t *iop = &immap->im_ioport;
  55. timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
  56. immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
  57. iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
  58. if ( atmMemInit() != OK ) return ERROR;
  59. atmIntInit();
  60. atmApcInit();
  61. atmAmtInit();
  62. atmCpmInit();
  63. atmUtpInit();
  64. g_atm.loaded = TRUE;
  65. return OK;
  66. }
  67. /*****************************************************************************
  68. *
  69. * FUNCTION NAME: atmUnload
  70. *
  71. * DESCRIPTION: Disables ATM and UTOPIA.
  72. *
  73. * PARAMETERS: none
  74. *
  75. * RETURNS: void
  76. *
  77. ****************************************************************************/
  78. void atmUnload()
  79. {
  80. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  81. volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
  82. volatile iop8xx_t *iop = &immap->im_ioport;
  83. timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */
  84. immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
  85. iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */
  86. g_atm.loaded = FALSE;
  87. }
  88. /*****************************************************************************
  89. *
  90. * FUNCTION NAME: atmMemInit
  91. *
  92. * DESCRIPTION:
  93. *
  94. * The ATM driver uses the following resources:
  95. *
  96. * A. Memory in DPRAM to hold
  97. *
  98. * 1/ CT = Connection Table ( RCT & TCT )
  99. * 2/ TCTE = Transmit Connection Table Extension
  100. * 3/ MPHYPT = Multi-PHY Pointing Table
  101. * 4/ APCP = APC Parameter Table
  102. * 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
  103. * 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
  104. * 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
  105. * 8/ TQ = Transmit Queue
  106. * 9/ AM = Address Matching Table
  107. * 10/ AP = Address Pointing Table
  108. *
  109. * B. Memory in cache safe RAM to hold
  110. *
  111. * 1/ INT = Interrupt Queue
  112. * 2/ RBD = Receive Buffer Descriptors
  113. * 3/ TBD = Transmit Buffer Descriptors
  114. *
  115. * This function
  116. * 1. clears the ATM DPRAM area,
  117. * 2. Allocates and clears cache safe memory,
  118. * 3. Initializes 'g_conn'.
  119. *
  120. * PARAMETERS: none
  121. *
  122. * RETURNS: OK or ERROR
  123. *
  124. ****************************************************************************/
  125. int atmMemInit()
  126. {
  127. int i;
  128. unsigned immr = CONFIG_SYS_IMMR;
  129. int total_num_rbd = 0;
  130. int total_num_tbd = 0;
  131. memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
  132. g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
  133. for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
  134. total_num_rbd += g_conn[i].num_rbd;
  135. total_num_tbd += g_conn[i].num_tbd;
  136. }
  137. g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
  138. g_atm.csram = &csram[0];
  139. memset(&(g_atm.csram), 0x00, g_atm.csram_size);
  140. g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4);
  141. g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
  142. g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
  143. g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
  144. g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
  145. g_conn[0].ct_ptr = CT_PTR(immr);
  146. g_conn[0].tcte_ptr = TCTE_PTR(immr);
  147. return OK;
  148. }
  149. /*****************************************************************************
  150. *
  151. * FUNCTION NAME: atmIntInit
  152. *
  153. * DESCRIPTION:
  154. *
  155. * Initialization of the MPC860 ESAR Interrupt Queue.
  156. * This function
  157. * - clears all entries in the INT,
  158. * - sets the WRAP bit of the last INT entry,
  159. * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
  160. * to the first INT entry.
  161. *
  162. * PARAMETERS: none
  163. *
  164. * RETURNS: void
  165. *
  166. * REMARKS:
  167. *
  168. * - The INT resides in external cache safe memory.
  169. * - The base address of the INT is stored in g_atm.int_reload_ptr.
  170. * - The number of entries in the INT is given by NUM_INT_ENTRIES.
  171. * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
  172. *
  173. ****************************************************************************/
  174. void atmIntInit()
  175. {
  176. int i;
  177. for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
  178. g_atm.int_reload_ptr[i] = INT_WRAP;
  179. g_atm.int_serv_ptr = g_atm.int_reload_ptr;
  180. }
  181. /*****************************************************************************
  182. *
  183. * FUNCTION NAME: atmApcInit
  184. *
  185. * DESCRIPTION:
  186. *
  187. * This function initializes the following ATM Pace Controller related
  188. * data structures:
  189. *
  190. * - 1 MPHY Pointing Table (contains only one entry)
  191. * - 3 APC Parameter Tables (one PHY with 3 priorities)
  192. * - 3 APC Tables (one table for each priority)
  193. * - 1 Transmit Queue (one transmit queue per PHY)
  194. *
  195. * PARAMETERS: none
  196. *
  197. * RETURNS: void
  198. *
  199. ****************************************************************************/
  200. void atmApcInit()
  201. {
  202. int i;
  203. /* unsigned immr = CONFIG_SYS_IMMR; */
  204. uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR);
  205. struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR);
  206. uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR);
  207. uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR);
  208. /***************************************************/
  209. /* Initialize MPHY Pointing Table (only one entry) */
  210. /***************************************************/
  211. *mphypt_ptr = APCP_BASE;
  212. /********************************************/
  213. /* Initialize APC parameters for priority 1 */
  214. /********************************************/
  215. apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
  216. apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
  217. apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE;
  218. apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
  219. apcp_ptr->etqbase = TQ_BASE;
  220. apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
  221. apcp_ptr->etqaptr = TQ_BASE;
  222. apcp_ptr->etqtptr = TQ_BASE;
  223. apcp_ptr->apc_mi = 8;
  224. apcp_ptr->ncits = 0x0100; /* NCITS = 1 */
  225. apcp_ptr->apcnt = 0;
  226. apcp_ptr->reserved1 = 0;
  227. apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */
  228. apcp_ptr->ptp_counter = 0;
  229. apcp_ptr->ptp_txch = 0;
  230. apcp_ptr->reserved2 = 0;
  231. /***************************************************/
  232. /* Initialize APC Tables with empty slots (0xFFFF) */
  233. /***************************************************/
  234. for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
  235. /************************/
  236. /* Clear Transmit Queue */
  237. /************************/
  238. for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
  239. }
  240. /*****************************************************************************
  241. *
  242. * FUNCTION NAME: atmAmtInit
  243. *
  244. * DESCRIPTION:
  245. *
  246. * This function clears the first entry in the Address Matching Table and
  247. * lets the first entry in the Address Pointing table point to the first
  248. * entry in the TCT table (i.e. the raw cell channel).
  249. *
  250. * PARAMETERS: none
  251. *
  252. * RETURNS: void
  253. *
  254. * REMARKS:
  255. *
  256. * The values for the AMBASE, AMEND and APBASE registers in SAR parameter
  257. * RAM are initialized by atmCpmInit().
  258. *
  259. ****************************************************************************/
  260. void atmAmtInit()
  261. {
  262. unsigned immr = CONFIG_SYS_IMMR;
  263. g_atm.am_top = AM_PTR(immr);
  264. g_atm.ap_top = AP_PTR(immr);
  265. *(g_atm.ap_top--) = CT_BASE;
  266. *(g_atm.am_top--) = 0;
  267. }
  268. /*****************************************************************************
  269. *
  270. * FUNCTION NAME: atmCpmInit
  271. *
  272. * DESCRIPTION:
  273. *
  274. * This function initializes the Utopia Interface Parameter RAM Map
  275. * (SCC4, ATM Protocol) of the Communication Processor Modudule.
  276. *
  277. * PARAMETERS: none
  278. *
  279. * RETURNS: void
  280. *
  281. ****************************************************************************/
  282. void atmCpmInit()
  283. {
  284. unsigned immr = CONFIG_SYS_IMMR;
  285. memset((char *)immr + 0x3F00, 0x00, 0xC0);
  286. /*-----------------------------------------------------------------*/
  287. /* RBDBASE - Receive buffer descriptors base address */
  288. /* The RBDs reside in cache safe external memory. */
  289. /*-----------------------------------------------------------------*/
  290. *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
  291. /*-----------------------------------------------------------------*/
  292. /* SRFCR - SAR receive function code */
  293. /* 0-2 rsvd = 000 */
  294. /* 3-4 BO = 11 Byte ordering (big endian). */
  295. /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
  296. /* when the SDMA channel accesses memory. */
  297. /*-----------------------------------------------------------------*/
  298. *SRFCR(immr) = 0x18;
  299. /*-----------------------------------------------------------------*/
  300. /* SRSTATE - SAR receive status */
  301. /* 0 EXT = 0 Extended mode off. */
  302. /* 1 ACP = 0 Valid only if EXT = 1. */
  303. /* 2 EC = 0 Standard 53-byte ATM cell. */
  304. /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */
  305. /* 4 ESAR = 1 Enhanced SAR functionality enabled. */
  306. /* 5 MCF = 1 Management Cell Filter active. */
  307. /* 6 SER = 0 UTOPIA mode. */
  308. /* 7 MPY = 1 Multiple PHY mode. */
  309. /*-----------------------------------------------------------------*/
  310. *SRSTATE(immr) = 0x0D;
  311. /*-----------------------------------------------------------------*/
  312. /* MRBLR - Maximum receive buffer length register. */
  313. /* Must be cleared for ATM operation (see also SMRBLR). */
  314. /*-----------------------------------------------------------------*/
  315. *MRBLR(immr) = 0;
  316. /*-----------------------------------------------------------------*/
  317. /* RSTATE - SCC internal receive state parameters */
  318. /* The first byte must be initialized with the value of SRFCR. */
  319. /*-----------------------------------------------------------------*/
  320. *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
  321. /*-----------------------------------------------------------------*/
  322. /* STFCR - SAR transmit function code */
  323. /* 0-2 rsvd = 000 */
  324. /* 3-4 BO = 11 Byte ordering (big endian). */
  325. /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */
  326. /* when the SDMA channel accesses memory. */
  327. /*-----------------------------------------------------------------*/
  328. *STFCR(immr) = 0x18;
  329. /*-----------------------------------------------------------------*/
  330. /* SRSTATE - SAR transmit status */
  331. /* 0 EXT = 0 : Extended mode off */
  332. /* 1 rsvd = 0 : */
  333. /* 2 EC = 0 : Standard 53-byte ATM cell */
  334. /* 3 rsvd = 0 : */
  335. /* 4 ESAR = 1 : Enhanced SAR functionality enabled */
  336. /* 5 rsvd = 0 : */
  337. /* 6 SER = 0 : UTOPIA mode */
  338. /* 7 MPY = 1 : Multiple PHY mode */
  339. /*-----------------------------------------------------------------*/
  340. *STSTATE(immr) = 0x09;
  341. /*-----------------------------------------------------------------*/
  342. /* TBDBASE - Transmit buffer descriptors base address */
  343. /* The TBDs reside in cache safe external memory. */
  344. /*-----------------------------------------------------------------*/
  345. *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
  346. /*-----------------------------------------------------------------*/
  347. /* TSTATE - SCC internal transmit state parameters */
  348. /* The first byte must be initialized with the value of STFCR. */
  349. /*-----------------------------------------------------------------*/
  350. *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
  351. /*-----------------------------------------------------------------*/
  352. /* CTBASE - Connection table base address */
  353. /* Offset from the beginning of DPRAM (64-byte aligned). */
  354. /*-----------------------------------------------------------------*/
  355. *CTBASE(immr) = CT_BASE;
  356. /*-----------------------------------------------------------------*/
  357. /* INTBASE - Interrupt queue base pointer. */
  358. /* The interrupt queue resides in cache safe external memory. */
  359. /*-----------------------------------------------------------------*/
  360. *INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
  361. /*-----------------------------------------------------------------*/
  362. /* INTPTR - Pointer into interrupt queue. */
  363. /* Initialize to INTBASE. */
  364. /*-----------------------------------------------------------------*/
  365. *INTPTR(immr) = *INTBASE(immr);
  366. /*-----------------------------------------------------------------*/
  367. /* C_MASK - Constant mask for CRC32 */
  368. /* Must be initialized to 0xDEBB20E3. */
  369. /*-----------------------------------------------------------------*/
  370. *C_MASK(immr) = 0xDEBB20E3;
  371. /*-----------------------------------------------------------------*/
  372. /* INT_ICNT - Interrupt threshold value */
  373. /*-----------------------------------------------------------------*/
  374. *INT_ICNT(immr) = 1;
  375. /*-----------------------------------------------------------------*/
  376. /* INT_CNT - Interrupt counter */
  377. /* Initalize to INT_ICNT. Decremented for each interrupt entry */
  378. /* reported in the interrupt queue. On zero an interrupt is */
  379. /* signaled to the host by setting the GINT bit in the event */
  380. /* register. The counter is reinitialized with INT_ICNT. */
  381. /*-----------------------------------------------------------------*/
  382. *INT_CNT(immr) = *INT_ICNT(immr);
  383. /*-----------------------------------------------------------------*/
  384. /* SMRBLR - SAR maximum receive buffer length register. */
  385. /* Must be a multiple of 48 bytes. Common for all ATM connections. */
  386. /*-----------------------------------------------------------------*/
  387. *SMRBLR(immr) = SAR_RXB_SIZE;
  388. /*-----------------------------------------------------------------*/
  389. /* APCST - APC status register. */
  390. /* 0 rsvd 0 */
  391. /* 1-2 CSER 11 Initialize with the same value as NSER. */
  392. /* 3-4 NSER 11 Next serial or UTOPIA channel. */
  393. /* 5-7 rsvd 000 */
  394. /* 8-10 rsvd 000 */
  395. /* 11 rsvd 0 */
  396. /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */
  397. /* 13 DIS 0 APC disable. Must be initiazed to 0. */
  398. /* 14 PL2 0 Not used. */
  399. /* 15 MPY 1 Multiple PHY mode on. */
  400. /*-----------------------------------------------------------------*/
  401. *APCST(immr) = 0x7809;
  402. /*-----------------------------------------------------------------*/
  403. /* APCPTR - Pointer to the APC parameter table */
  404. /* In MPHY master mode this parameter points to the MPHY pointing */
  405. /* table. 2-byte aligned. */
  406. /*-----------------------------------------------------------------*/
  407. *APCPTR(immr) = MPHYPT_BASE;
  408. /*-----------------------------------------------------------------*/
  409. /* HMASK - Header mask */
  410. /* Each incoming cell is masked with HMASK before being compared */
  411. /* to the entries in the address matching table. */
  412. /*-----------------------------------------------------------------*/
  413. *HMASK(immr) = AM_HMASK;
  414. /*-----------------------------------------------------------------*/
  415. /* AMBASE - Address matching table base address */
  416. /*-----------------------------------------------------------------*/
  417. *AMBASE(immr) = AM_BASE;
  418. /*-----------------------------------------------------------------*/
  419. /* AMEND - Address matching table end address */
  420. /*-----------------------------------------------------------------*/
  421. *AMEND(immr) = AM_BASE;
  422. /*-----------------------------------------------------------------*/
  423. /* APBASE - Address pointing table base address */
  424. /*-----------------------------------------------------------------*/
  425. *APBASE(immr) = AP_BASE;
  426. /*-----------------------------------------------------------------*/
  427. /* MPHYST - MPHY status register */
  428. /* 0-1 rsvd 00 */
  429. /* 2-6 NMPHY 00000 1 PHY */
  430. /* 7-9 rsvd 000 */
  431. /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */
  432. /*-----------------------------------------------------------------*/
  433. *MPHYST(immr) = 0x0000;
  434. /*-----------------------------------------------------------------*/
  435. /* TCTEBASE - Transmit connection table extension base address */
  436. /* Offset from the beginning of DPRAM (32-byte aligned). */
  437. /*-----------------------------------------------------------------*/
  438. *TCTEBASE(immr) = TCTE_BASE;
  439. /*-----------------------------------------------------------------*/
  440. /* Clear not used registers. */
  441. /*-----------------------------------------------------------------*/
  442. }
  443. /*****************************************************************************
  444. *
  445. * FUNCTION NAME: atmUtpInit
  446. *
  447. * DESCRIPTION:
  448. *
  449. * This function initializes the ATM interface for
  450. *
  451. * - UTOPIA mode
  452. * - muxed bus
  453. * - master operation
  454. * - multi PHY (because of a bug in the MPC860P rev. E.0)
  455. * - internal clock = SYSCLK / 2
  456. *
  457. * EXTERNAL EFFECTS:
  458. *
  459. * After calling this function, the MPC860ESAR UTOPIA bus is
  460. * active and uses the following ports/pins:
  461. *
  462. * Port Pin Signal Description
  463. * ------ --- ------- -------------------------------------------
  464. * PB[15] R17 TxClav Transmit cell available input/output signal
  465. * PC[15] D16 RxClav Receive cell available input/output signal
  466. * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal
  467. * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal
  468. * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal
  469. * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal
  470. * PD[11] T16 RXENB Receive enable input/output signal
  471. * PD[10] W18 TXENB Transmit enable input/output signal
  472. * PD[9] V17 UTPCLK UTOPIA clock input/output signal
  473. * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal
  474. * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal
  475. * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal
  476. * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal
  477. * PD[3] W16 SOC Start of cell input/output signal
  478. *
  479. * PARAMETERS: none
  480. *
  481. * RETURNS: void
  482. *
  483. * REMARK:
  484. *
  485. * The ATM parameters and data structures must be configured before
  486. * initializing the UTOPIA port. The UTOPIA port activates immediately
  487. * upon initialization, and if its associated data structures are not
  488. * initialized, the CPM will lock up.
  489. *
  490. ****************************************************************************/
  491. void atmUtpInit()
  492. {
  493. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  494. volatile iop8xx_t *iop = &immap->im_ioport;
  495. volatile car8xx_t *car = &immap->im_clkrst;
  496. volatile cpm8xx_t *cpm = &immap->im_cpm;
  497. int flag;
  498. flag = disable_interrupts();
  499. /*-----------------------------------------------------------------*/
  500. /* SCCR - System Clock Control Register */
  501. /* */
  502. /* The UTOPIA clock can be selected to be internal clock or */
  503. /* external clock (selected by the UTOPIA mode register). */
  504. /* In case of internal clock, the UTOPIA clock is derived from */
  505. /* the system frequency divided by two dividers. */
  506. /* Bits 27-31 of the SCCR register are defined to control the */
  507. /* UTOPIA clock. */
  508. /* */
  509. /* SCCR[27:29] DFUTP Division factor. Divide the system clock */
  510. /* by 2^DFUTP. */
  511. /* SCCR[30:31] DFAUTP Additional division factor. Divide the */
  512. /* system clock by the following value: */
  513. /* 00 = divide by 1 */
  514. /* 00 = divide by 3 */
  515. /* 10 = divide by 5 */
  516. /* 11 = divide by 7 */
  517. /* */
  518. /* Note that the UTOPIA clock must be programmed as to operate */
  519. /* within the range SYSCLK/10 .. 50MHz. */
  520. /*-----------------------------------------------------------------*/
  521. car->car_sccr &= 0xFFFFFFE0;
  522. car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
  523. /*-----------------------------------------------------------------*/
  524. /* RCCR - RISC Controller Configuration Register */
  525. /* */
  526. /* RCCR[8] DR1M IDMA Request 0 Mode */
  527. /* 0 = edge sensitive */
  528. /* 1 = level sensitive */
  529. /* RCCR[9] DR0M IDMA Request 0 Mode */
  530. /* 0 = edge sensitive */
  531. /* 1 = level sensitive */
  532. /* RCCR[10:11] DRQP IDMA Request Priority */
  533. /* 00 = IDMA req. have more prio. than SCCs */
  534. /* 01 = IDMA req. have less prio. then SCCs */
  535. /* 10 = IDMA requests have the lowest prio. */
  536. /* 11 = reserved */
  537. /* */
  538. /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
  539. /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
  540. /* higher priority. */
  541. /*-----------------------------------------------------------------*/
  542. cpm->cp_rccr &= 0xFF0F;
  543. cpm->cp_rccr |= 0x00D0;
  544. /*-----------------------------------------------------------------*/
  545. /* Port B - TxClav Signal */
  546. /*-----------------------------------------------------------------*/
  547. cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
  548. cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
  549. /*-----------------------------------------------------------------*/
  550. /* UTOPIA Mode Register */
  551. /* */
  552. /* - muxed bus (master operation only) */
  553. /* - multi PHY (because of a bug in the MPC860P rev.E.0) */
  554. /* - internal clock */
  555. /* - no loopback */
  556. /* - do no activate statistical counters */
  557. /*-----------------------------------------------------------------*/
  558. iop->utmode = 0x00000004; SYNC;
  559. /*-----------------------------------------------------------------*/
  560. /* Port D - UTOPIA Data and Control Signals */
  561. /* */
  562. /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */
  563. /* 11 RXENB UTOPIA receive enable input/output signal */
  564. /* 10 TXENB UTOPIA transmit enable input/output signal */
  565. /* 9 TUPCLK UTOPIA clock input/output signal */
  566. /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */
  567. /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */
  568. /* 3 SOC UTOPIA Start of cell input/output signal */
  569. /* 2 Reserved */
  570. /* 1 Enable UTOPIA mode */
  571. /* 0 Enable SAR */
  572. /*-----------------------------------------------------------------*/
  573. iop->iop_pdpar |= 0xDF7F; SYNC;
  574. iop->iop_pddir &= 0x2080; SYNC;
  575. /*-----------------------------------------------------------------*/
  576. /* Port C - RxClav Signal */
  577. /*-----------------------------------------------------------------*/
  578. iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */
  579. iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */
  580. iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */
  581. if (flag)
  582. enable_interrupts();
  583. }