codec.c 42 KB

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  1. /*
  2. * CODEC
  3. */
  4. #include <common.h>
  5. #include <post.h>
  6. #include "mpc8xx.h"
  7. /***********************************************/
  8. #define MAX_DUSLIC 4
  9. #define NUM_CHANNELS 2
  10. #define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS)
  11. /***********************************************/
  12. #define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */
  13. #define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */
  14. #define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */
  15. #define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */
  16. #define COP_READ_CH_0 0xC5
  17. #define COP_READ_CH_1 0xCD
  18. #define COP_WRITE_CH_0 0x45
  19. #define COP_WRITE_CH_1 0x4D
  20. #define POP_READ_CH_0 0xC6
  21. #define POP_READ_CH_1 0xCE
  22. #define POP_WRITE_CH_0 0x46
  23. #define POP_WRITE_CH_1 0x4E
  24. #define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */
  25. #define RST_CMD_DUSLIC_CH_A 0x41
  26. #define RST_CMD_DUSLIC_CH_B 0x49
  27. #define PCM_RESYNC_CMD_CH_A 0x42
  28. #define PCM_RESYNC_CMD_CH_B 0x4A
  29. #define ACTIVE_HOOK_LEV_4 0
  30. #define ACTIVE_HOOK_LEV_12 1
  31. #define SLIC_P_NORMAL 0x01
  32. /************************************************/
  33. #define CODSP_WR 0x00
  34. #define CODSP_RD 0x80
  35. #define CODSP_OP 0x40
  36. #define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3)
  37. #define CODSP_M(x) ((unsigned char)(x) & 7)
  38. #define CODSP_CMD(x) ((unsigned char)(x) & 7)
  39. /************************************************/
  40. /* command indication ops */
  41. #define CODSP_M_SLEEP_PWRDN 7
  42. #define CODSP_M_PWRDN_HIZ 0
  43. #define CODSP_M_ANY_ACT 2
  44. #define CODSP_M_RING 5
  45. #define CODSP_M_ACT_MET 6
  46. #define CODSP_M_GND_START 4
  47. #define CODSP_M_RING_PAUSE 1
  48. /* single byte commands */
  49. #define CODSP_CMD_SOFT_RESET CODSP_CMD(0)
  50. #define CODSP_CMD_RESET_CH CODSP_CMD(1)
  51. #define CODSP_CMD_RESYNC CODSP_CMD(2)
  52. /* two byte commands */
  53. #define CODSP_CMD_SOP CODSP_CMD(4)
  54. #define CODSP_CMD_COP CODSP_CMD(5)
  55. #define CODSP_CMD_POP CODSP_CMD(6)
  56. /************************************************/
  57. /* read as 4-bytes */
  58. #define CODSP_INTREG_INT_CH 0x80000000
  59. #define CODSP_INTREG_HOOK 0x40000000
  60. #define CODSP_INTREG_GNDK 0x20000000
  61. #define CODSP_INTREG_GNDP 0x10000000
  62. #define CODSP_INTREG_ICON 0x08000000
  63. #define CODSP_INTREG_VRTLIM 0x04000000
  64. #define CODSP_INTREG_OTEMP 0x02000000
  65. #define CODSP_INTREG_SYNC_FAIL 0x01000000
  66. #define CODSP_INTREG_LM_THRES 0x00800000
  67. #define CODSP_INTREG_READY 0x00400000
  68. #define CODSP_INTREG_RSTAT 0x00200000
  69. #define CODSP_INTREG_LM_OK 0x00100000
  70. #define CODSP_INTREG_IO4_DU 0x00080000
  71. #define CODSP_INTREG_IO3_DU 0x00040000
  72. #define CODSP_INTREG_IO2_DU 0x00020000
  73. #define CODSP_INTREG_IO1_DU 0x00010000
  74. #define CODSP_INTREG_DTMF_OK 0x00008000
  75. #define CODSP_INTREG_DTMF_KEY4 0x00004000
  76. #define CODSP_INTREG_DTMF_KEY3 0x00002000
  77. #define CODSP_INTREG_DTMF_KEY2 0x00001000
  78. #define CODSP_INTREG_DTMF_KEY1 0x00000800
  79. #define CODSP_INTREG_DTMF_KEY0 0x00000400
  80. #define CODSP_INTREG_UTDR_OK 0x00000200
  81. #define CODSP_INTREG_UTDX_OK 0x00000100
  82. #define CODSP_INTREG_EDSP_FAIL 0x00000080
  83. #define CODSP_INTREG_CIS_BOF 0x00000008
  84. #define CODSP_INTREG_CIS_BUF 0x00000004
  85. #define CODSP_INTREG_CIS_REQ 0x00000002
  86. #define CODSP_INTREG_CIS_ACT 0x00000001
  87. /************************************************/
  88. /* ======== SOP REG ADDRESSES =======*/
  89. #define REVISION_ADDR 0x00
  90. #define PCMC1_ADDR 0x05
  91. #define XCR_ADDR 0x06
  92. #define INTREG1_ADDR 0x07
  93. #define INTREG2_ADDR 0x08
  94. #define INTREG3_ADDR 0x09
  95. #define INTREG4_ADDR 0x0A
  96. #define LMRES1_ADDR 0x0D
  97. #define MASK_ADDR 0x11
  98. #define IOCTL3_ADDR 0x14
  99. #define BCR1_ADDR 0x15
  100. #define BCR2_ADDR 0x16
  101. #define BCR3_ADDR 0x17
  102. #define BCR4_ADDR 0x18
  103. #define BCR5_ADDR 0x19
  104. #define DSCR_ADDR 0x1A
  105. #define LMCR1_ADDR 0x1C
  106. #define LMCR2_ADDR 0x1D
  107. #define LMCR3_ADDR 0x1E
  108. #define OFR1_ADDR 0x1F
  109. #define PCMR1_ADDR 0x21
  110. #define PCMX1_ADDR 0x25
  111. #define TSTR3_ADDR 0x2B
  112. #define TSTR4_ADDR 0x2C
  113. #define TSTR5_ADDR 0x2D
  114. /* ========= POP REG ADDRESSES ========*/
  115. #define CIS_DAT_ADDR 0x00
  116. #define LEC_LEN_ADDR 0x3A
  117. #define LEC_POWR_ADDR 0x3B
  118. #define LEC_DELP_ADDR 0x3C
  119. #define LEC_DELQ_ADDR 0x3D
  120. #define LEC_GAIN_XI_ADDR 0x3E
  121. #define LEC_GAIN_RI_ADDR 0x3F
  122. #define LEC_GAIN_XO_ADDR 0x40
  123. #define LEC_RES_1_ADDR 0x41
  124. #define LEC_RES_2_ADDR 0x42
  125. #define NLP_POW_LPF_ADDR 0x30
  126. #define NLP_POW_LPS_ADDR 0x31
  127. #define NLP_BN_LEV_X_ADDR 0x32
  128. #define NLP_BN_LEV_R_ADDR 0x33
  129. #define NLP_BN_INC_ADDR 0x34
  130. #define NLP_BN_DEC_ADDR 0x35
  131. #define NLP_BN_MAX_ADDR 0x36
  132. #define NLP_BN_ADJ_ADDR 0x37
  133. #define NLP_RE_MIN_ERLL_ADDR 0x38
  134. #define NLP_RE_EST_ERLL_ADDR 0x39
  135. #define NLP_SD_LEV_X_ADDR 0x3A
  136. #define NLP_SD_LEV_R_ADDR 0x3B
  137. #define NLP_SD_LEV_BN_ADDR 0x3C
  138. #define NLP_SD_LEV_RE_ADDR 0x3D
  139. #define NLP_SD_OT_DT_ADDR 0x3E
  140. #define NLP_ERL_LIN_LP_ADDR 0x3F
  141. #define NLP_ERL_LEC_LP_ADDR 0x40
  142. #define NLP_CT_LEV_RE_ADDR 0x41
  143. #define NLP_CTRL_ADDR 0x42
  144. #define UTD_CF_H_ADDR 0x4B
  145. #define UTD_CF_L_ADDR 0x4C
  146. #define UTD_BW_H_ADDR 0x4D
  147. #define UTD_BW_L_ADDR 0x4E
  148. #define UTD_NLEV_ADDR 0x4F
  149. #define UTD_SLEV_H_ADDR 0x50
  150. #define UTD_SLEV_L_ADDR 0x51
  151. #define UTD_DELT_ADDR 0x52
  152. #define UTD_RBRK_ADDR 0x53
  153. #define UTD_RTIME_ADDR 0x54
  154. #define UTD_EBRK_ADDR 0x55
  155. #define UTD_ETIME_ADDR 0x56
  156. #define DTMF_LEV_ADDR 0x30
  157. #define DTMF_TWI_ADDR 0x31
  158. #define DTMF_NCF_H_ADDR 0x32
  159. #define DTMF_NCF_L_ADDR 0x33
  160. #define DTMF_NBW_H_ADDR 0x34
  161. #define DTMF_NBW_L_ADDR 0x35
  162. #define DTMF_GAIN_ADDR 0x36
  163. #define DTMF_RES1_ADDR 0x37
  164. #define DTMF_RES2_ADDR 0x38
  165. #define DTMF_RES3_ADDR 0x39
  166. #define CIS_LEV_H_ADDR 0x43
  167. #define CIS_LEV_L_ADDR 0x44
  168. #define CIS_BRS_ADDR 0x45
  169. #define CIS_SEIZ_H_ADDR 0x46
  170. #define CIS_SEIZ_L_ADDR 0x47
  171. #define CIS_MARK_H_ADDR 0x48
  172. #define CIS_MARK_L_ADDR 0x49
  173. #define CIS_LEC_MODE_ADDR 0x4A
  174. /*=====================================*/
  175. #define HOOK_LEV_ACT_START_ADDR 0x89
  176. #define RO1_START_ADDR 0x70
  177. #define RO2_START_ADDR 0x95
  178. #define RO3_START_ADDR 0x96
  179. #define TG1_FREQ_START_ADDR 0x38
  180. #define TG1_GAIN_START_ADDR 0x39
  181. #define TG1_BANDPASS_START_ADDR 0x3B
  182. #define TG1_BANDPASS_END_ADDR 0x3D
  183. #define TG2_FREQ_START_ADDR 0x40
  184. #define TG2_GAIN_START_ADDR 0x41
  185. #define TG2_BANDPASS_START_ADDR 0x43
  186. #define TG2_BANDPASS_END_ADDR 0x45
  187. /*====================================*/
  188. #define PCM_HW_B 0x80
  189. #define PCM_HW_A 0x00
  190. #define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */
  191. #define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */
  192. #define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
  193. #define RX_LEV_ADDR 0x28
  194. #define TX_LEV_ADDR 0x30
  195. #define Ik1_ADDR 0x83
  196. #define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */
  197. #define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */
  198. #define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
  199. /* Mark the start byte of Duslic parameters that we use with configurator */
  200. #define Ik1_START_BYTE 3
  201. #define RX_LEV_START_BYTE 0
  202. #define TX_LEV_START_BYTE 0
  203. /************************************************/
  204. #define INTREG4_CIS_ACT (1 << 0)
  205. #define BCR1_SLEEP 0x20
  206. #define BCR1_REVPOL 0x10
  207. #define BCR1_ACTR 0x08
  208. #define BCR1_ACTL 0x04
  209. #define BCR1_SLIC_MASK 0x03
  210. #define BCR2_HARD_POL_REV 0x40
  211. #define BCR2_TTX 0x20
  212. #define BCR2_TTX_12K 0x10
  213. #define BCR2_HIMAN 0x08
  214. #define BCR2_PDOT 0x01
  215. #define BCR3_PCMX_EN (1 << 4)
  216. #define BCR5_DTMF_EN (1 << 0)
  217. #define BCR5_DTMF_SRC (1 << 1)
  218. #define BCR5_LEC_EN (1 << 2)
  219. #define BCR5_LEC_OUT (1 << 3)
  220. #define BCR5_CIS_EN (1 << 4)
  221. #define BCR5_CIS_AUTO (1 << 5)
  222. #define BCR5_UTDX_EN (1 << 6)
  223. #define BCR5_UTDR_EN (1 << 7)
  224. #define DSCR_TG1_EN (1 << 0)
  225. #define DSCR_TG2_EN (1 << 1)
  226. #define DSCR_PTG (1 << 2)
  227. #define DSCR_COR8 (1 << 3)
  228. #define DSCR_DG_KEY(x) (((x) & 0x0F) << 4)
  229. #define CIS_LEC_MODE_CIS_V23 (1 << 0)
  230. #define CIS_LEC_MODE_CIS_FRM (1 << 1)
  231. #define CIS_LEC_MODE_NLP_EN (1 << 2)
  232. #define CIS_LEC_MODE_UTDR_SUM (1 << 4)
  233. #define CIS_LEC_MODE_UTDX_SUM (1 << 5)
  234. #define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
  235. #define CIS_LEC_MODE_LEC_ADAPT (1 << 7)
  236. #define TSTR4_COR_64 (1 << 5)
  237. #define TSTR3_AC_DLB_8K (1 << 2)
  238. #define TSTR3_AC_DLB_32K (1 << 3)
  239. #define TSTR3_AC_DLB_4M (1 << 5)
  240. #define LMCR1_TEST_EN (1 << 7)
  241. #define LMCR1_LM_EN (1 << 6)
  242. #define LMCR1_LM_THM (1 << 5)
  243. #define LMCR1_LM_ONCE (1 << 2)
  244. #define LMCR1_LM_MASK (1 << 1)
  245. #define LMCR2_LM_RECT (1 << 5)
  246. #define LMCR2_LM_SEL_VDD 0x0D
  247. #define LMCR2_LM_SEL_IO3 0x0A
  248. #define LMCR2_LM_SEL_IO4 0x0B
  249. #define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F
  250. #define LMCR3_RTR_SEL (1 << 6)
  251. #define LMCR3_RNG_OFFSET_NONE 0x00
  252. #define LMCR3_RNG_OFFSET_1 0x01
  253. #define LMCR3_RNG_OFFSET_2 0x02
  254. #define LMCR3_RNG_OFFSET_3 0x03
  255. #define TSTR5_DC_HOLD (1 << 3)
  256. /************************************************/
  257. #define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */
  258. #define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */
  259. #define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */
  260. #define DIVIDER_RATIO_ACCURx100 (22 * 100)
  261. #define V_AD_x10000 10834L /* VAD = 1.0834 */
  262. #define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */
  263. #define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */
  264. #define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/
  265. #define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */
  266. #define K_INTDC_RECT_OFF 2 /* 2^2 */
  267. #define RNG_FREQ 25
  268. #define SAMPLING_FREQ (2000L)
  269. #define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
  270. #define HOOK_THRESH_RING_START_ADDR 0x8B
  271. #define RING_PARAMS_START_ADDR 0x70
  272. #define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */
  273. #define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */
  274. #define MAX_V_RING_MEANx100 50
  275. #define TARGET_V_RING_RMSx100 2720
  276. #define V_RMS_RING_MAX_DIFFx100 250
  277. #define LM_OK_SRC_IRG_2 (1 << 4)
  278. /************************************************/
  279. #define PORTB (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
  280. #define PORTC (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
  281. #define PORTD (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
  282. #define _PORTD_SET(mask, state) \
  283. do { \
  284. if (state) \
  285. PORTD |= mask; \
  286. else \
  287. PORTD &= ~mask; \
  288. } while (0)
  289. #define _PORTB_SET(mask, state) \
  290. do { \
  291. if (state) \
  292. PORTB |= mask; \
  293. else \
  294. PORTB &= ~mask; \
  295. } while (0)
  296. #define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
  297. #define _PORTB_GET(mask) (!!(PORTB & mask))
  298. #define _PORTC_GET(mask) (!!(PORTC & mask))
  299. /* port B */
  300. #define SPI_RXD (1 << (31 - 28))
  301. #define SPI_TXD (1 << (31 - 29))
  302. #define SPI_CLK (1 << (31 - 30))
  303. /* port C */
  304. #define COM_HOOK1 (1 << (15 - 9))
  305. #define COM_HOOK2 (1 << (15 - 10))
  306. #ifndef CONFIG_NETTA_SWAPHOOK
  307. #define COM_HOOK3 (1 << (15 - 11))
  308. #define COM_HOOK4 (1 << (15 - 12))
  309. #else
  310. #define COM_HOOK3 (1 << (15 - 12))
  311. #define COM_HOOK4 (1 << (15 - 11))
  312. #endif
  313. /* port D */
  314. #define SPIENC1 (1 << (15 - 9))
  315. #define SPIENC2 (1 << (15 - 10))
  316. #define SPIENC3 (1 << (15 - 11))
  317. #define SPIENC4 (1 << (15 - 14))
  318. #define SPI_DELAY() udelay(1)
  319. static inline unsigned int __SPI_Transfer(unsigned int tx)
  320. {
  321. unsigned int rx;
  322. int b;
  323. rx = 0; b = 8;
  324. while (--b >= 0) {
  325. _PORTB_SET(SPI_TXD, tx & 0x80);
  326. tx <<= 1;
  327. _PORTB_TGL(SPI_CLK);
  328. SPI_DELAY();
  329. rx <<= 1;
  330. rx |= _PORTB_GET(SPI_RXD);
  331. _PORTB_TGL(SPI_CLK);
  332. SPI_DELAY();
  333. }
  334. return rx;
  335. }
  336. static const char *codsp_dtmf_map = "D1234567890*#ABC";
  337. static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
  338. static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };
  339. static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen)
  340. {
  341. unsigned int rx;
  342. int i;
  343. /* just some sanity checks */
  344. if (cmd == 0 || cmdlen < 0)
  345. return -1;
  346. _PORTD_SET(spienc_mask_tab[duslic_id], 0);
  347. /* first 2 bytes are without response */
  348. i = 2;
  349. while (i-- > 0 && cmdlen-- > 0)
  350. __SPI_Transfer(*cmd++);
  351. while (cmdlen-- > 0) {
  352. rx = __SPI_Transfer(*cmd++);
  353. if (res != 0 && reslen-- > 0)
  354. *res++ = (unsigned char)rx;
  355. }
  356. if (res != 0) {
  357. while (reslen-- > 0)
  358. *res++ = __SPI_Transfer(0xFF);
  359. }
  360. _PORTD_SET(spienc_mask_tab[duslic_id], 1);
  361. return 0;
  362. }
  363. /****************************************************************************/
  364. void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
  365. {
  366. unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m);
  367. codsp_send(duslic_id, &cmd, 1, 0, 0);
  368. }
  369. void codsp_reset_chip(int duslic_id)
  370. {
  371. static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET;
  372. codsp_send(duslic_id, &cmd, 1, 0, 0);
  373. }
  374. void codsp_reset_channel(int duslic_id, int channel)
  375. {
  376. unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH;
  377. codsp_send(duslic_id, &cmd, 1, 0, 0);
  378. }
  379. void codsp_resync_channel(int duslic_id, int channel)
  380. {
  381. unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC;
  382. codsp_send(duslic_id, &cmd, 1, 0, 0);
  383. }
  384. /****************************************************************************/
  385. void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
  386. {
  387. unsigned char cmd[3];
  388. cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
  389. cmd[1] = regno;
  390. cmd[2] = val;
  391. codsp_send(duslic_id, cmd, 3, 0, 0);
  392. }
  393. void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
  394. {
  395. unsigned char cmd[4];
  396. cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
  397. cmd[1] = regno;
  398. cmd[2] = (unsigned char)(val >> 8);
  399. cmd[3] = (unsigned char)val;
  400. codsp_send(duslic_id, cmd, 4, 0, 0);
  401. }
  402. void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
  403. {
  404. unsigned char cmd[6];
  405. cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP;
  406. cmd[1] = regno;
  407. cmd[2] = (unsigned char)(val >> 24);
  408. cmd[3] = (unsigned char)(val >> 16);
  409. cmd[4] = (unsigned char)(val >> 8);
  410. cmd[5] = (unsigned char)val;
  411. codsp_send(duslic_id, cmd, 6, 0, 0);
  412. }
  413. unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)
  414. {
  415. unsigned char cmd[3];
  416. unsigned char res[2];
  417. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
  418. cmd[1] = regno;
  419. codsp_send(duslic_id, cmd, 2, res, 2);
  420. return res[1];
  421. }
  422. unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)
  423. {
  424. unsigned char cmd[2];
  425. unsigned char res[3];
  426. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
  427. cmd[1] = regno;
  428. codsp_send(duslic_id, cmd, 2, res, 3);
  429. return ((unsigned short)res[1] << 8) | res[2];
  430. }
  431. unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)
  432. {
  433. unsigned char cmd[2];
  434. unsigned char res[5];
  435. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
  436. cmd[1] = regno;
  437. codsp_send(duslic_id, cmd, 2, res, 5);
  438. return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
  439. }
  440. /****************************************************************************/
  441. void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)
  442. {
  443. unsigned char cmd[10];
  444. cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
  445. cmd[1] = addr;
  446. memcpy(cmd + 2, block, 8);
  447. codsp_send(duslic_id, cmd, 10, 0, 0);
  448. }
  449. void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)
  450. {
  451. unsigned char cmd[3];
  452. cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
  453. cmd[1] = addr;
  454. cmd[2] = val;
  455. codsp_send(duslic_id, cmd, 3, 0, 0);
  456. }
  457. void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)
  458. {
  459. unsigned char cmd[4];
  460. cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
  461. cmd[1] = addr;
  462. cmd[2] = (unsigned char)(val >> 8);
  463. cmd[3] = (unsigned char)val;
  464. codsp_send(duslic_id, cmd, 4, 0, 0);
  465. }
  466. void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)
  467. {
  468. unsigned char cmd[2];
  469. unsigned char res[9];
  470. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
  471. cmd[1] = addr;
  472. codsp_send(duslic_id, cmd, 2, res, 9);
  473. memcpy(block, res + 1, 8);
  474. }
  475. unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)
  476. {
  477. unsigned char cmd[2];
  478. unsigned char res[2];
  479. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
  480. cmd[1] = addr;
  481. codsp_send(duslic_id, cmd, 2, res, 2);
  482. return res[1];
  483. }
  484. unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)
  485. {
  486. unsigned char cmd[2];
  487. unsigned char res[3];
  488. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
  489. cmd[1] = addr;
  490. codsp_send(duslic_id, cmd, 2, res, 3);
  491. return ((unsigned short)res[1] << 8) | res[2];
  492. }
  493. /****************************************************************************/
  494. #define MAX_POP_BLOCK 50
  495. void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,
  496. const unsigned char *block, int len)
  497. {
  498. unsigned char cmd[2 + MAX_POP_BLOCK];
  499. if (len > MAX_POP_BLOCK) /* truncate */
  500. len = MAX_POP_BLOCK;
  501. cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
  502. cmd[1] = addr;
  503. memcpy (cmd + 2, block, len);
  504. codsp_send (duslic_id, cmd, 2 + len, 0, 0);
  505. }
  506. void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,
  507. unsigned char val)
  508. {
  509. unsigned char cmd[3];
  510. cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
  511. cmd[1] = regno;
  512. cmd[2] = val;
  513. codsp_send (duslic_id, cmd, 3, 0, 0);
  514. }
  515. void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,
  516. unsigned short val)
  517. {
  518. unsigned char cmd[4];
  519. cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
  520. cmd[1] = regno;
  521. cmd[2] = (unsigned char) (val >> 8);
  522. cmd[3] = (unsigned char) val;
  523. codsp_send (duslic_id, cmd, 4, 0, 0);
  524. }
  525. void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,
  526. unsigned int val)
  527. {
  528. unsigned char cmd[6];
  529. cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP;
  530. cmd[1] = regno;
  531. cmd[2] = (unsigned char) (val >> 24);
  532. cmd[3] = (unsigned char) (val >> 16);
  533. cmd[4] = (unsigned char) (val >> 8);
  534. cmd[5] = (unsigned char) val;
  535. codsp_send (duslic_id, cmd, 6, 0, 0);
  536. }
  537. unsigned char codsp_read_pop_char (int duslic_id, int channel,
  538. unsigned char regno)
  539. {
  540. unsigned char cmd[3];
  541. unsigned char res[2];
  542. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
  543. cmd[1] = regno;
  544. codsp_send (duslic_id, cmd, 2, res, 2);
  545. return res[1];
  546. }
  547. unsigned short codsp_read_pop_short (int duslic_id, int channel,
  548. unsigned char regno)
  549. {
  550. unsigned char cmd[2];
  551. unsigned char res[3];
  552. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
  553. cmd[1] = regno;
  554. codsp_send (duslic_id, cmd, 2, res, 3);
  555. return ((unsigned short) res[1] << 8) | res[2];
  556. }
  557. unsigned int codsp_read_pop_int (int duslic_id, int channel,
  558. unsigned char regno)
  559. {
  560. unsigned char cmd[2];
  561. unsigned char res[5];
  562. cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
  563. cmd[1] = regno;
  564. codsp_send (duslic_id, cmd, 2, res, 5);
  565. return (((unsigned int) res[1] << 24) |
  566. ((unsigned int) res[2] << 16) |
  567. ((unsigned int) res[3] << 8) |
  568. res[4] );
  569. }
  570. /****************************************************************************/
  571. struct _coeffs {
  572. unsigned char addr;
  573. unsigned char values[8];
  574. };
  575. struct _coeffs ac_coeffs[11] = {
  576. { 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
  577. { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
  578. { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */
  579. { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */
  580. { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */
  581. { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */
  582. { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */
  583. { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */
  584. { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
  585. { 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
  586. { 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */
  587. };
  588. struct _coeffs ac_coeffs_0dB[11] = {
  589. { 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },
  590. { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },
  591. { 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },
  592. { 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },
  593. { 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },
  594. { 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },
  595. { 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },
  596. { 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },
  597. { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },
  598. { 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },
  599. { 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }
  600. };
  601. struct _coeffs dc_coeffs[9] = {
  602. { 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */
  603. { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */
  604. { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */
  605. { 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */
  606. { 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */
  607. { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */
  608. { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */
  609. { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */
  610. { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */
  611. };
  612. void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
  613. {
  614. int i;
  615. for (i = 0; i < tab_size; i++)
  616. codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
  617. }
  618. #define SS_OPEN_CIRCUIT 0
  619. #define SS_RING_PAUSE 1
  620. #define SS_ACTIVE 2
  621. #define SS_ACTIVE_HIGH 3
  622. #define SS_ACTIVE_RING 4
  623. #define SS_RINGING 5
  624. #define SS_ACTIVE_WITH_METERING 6
  625. #define SS_ONHOOKTRNSM 7
  626. #define SS_STANDBY 8
  627. #define SS_MAX 8
  628. static void codsp_set_slic(int duslic_id, int channel, int state)
  629. {
  630. unsigned char v;
  631. v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);
  632. switch (state) {
  633. case SS_ACTIVE:
  634. codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL);
  635. codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
  636. break;
  637. case SS_ACTIVE_HIGH:
  638. codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL));
  639. codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
  640. break;
  641. case SS_ACTIVE_RING:
  642. case SS_ONHOOKTRNSM:
  643. codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
  644. codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
  645. break;
  646. case SS_STANDBY:
  647. codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR));
  648. codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);
  649. break;
  650. case SS_OPEN_CIRCUIT:
  651. codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);
  652. break;
  653. case SS_RINGING:
  654. codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);
  655. break;
  656. case SS_RING_PAUSE:
  657. codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);
  658. break;
  659. }
  660. }
  661. const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };
  662. const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };
  663. void retrieve_slic_state(int slic_id)
  664. {
  665. int duslic_id = slic_id >> 1;
  666. int channel = slic_id & 1;
  667. /* Retrieve the state of the SLICs */
  668. codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
  669. /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
  670. udelay(10000);
  671. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
  672. codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
  673. codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);
  674. /* Program Default Hook Ring thresholds */
  675. codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);
  676. /* Now program Hook Threshold while Ring and ac RingTrip to max values */
  677. codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);
  678. codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
  679. udelay(40000);
  680. }
  681. int wait_level_metering_finish(int duslic_id, int channel)
  682. {
  683. int cnt;
  684. for (cnt = 0; cnt < 1000 &&
  685. (codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }
  686. return cnt != 1000;
  687. }
  688. int measure_on_hook_voltages(int slic_id, long *vdd,
  689. long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
  690. {
  691. short LM_Result, Offset_Compensation; /* Signed 16 bit */
  692. long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
  693. unsigned char err_mask = 0;
  694. int duslic_id = slic_id >> 1;
  695. int channel = slic_id & 1;
  696. int i;
  697. /* measure VDD */
  698. /* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */
  699. codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);
  700. /* Activate Test Mode ==> To Enable DC Hold !!! */
  701. /* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */
  702. /* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/
  703. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
  704. udelay(40000);
  705. /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
  706. codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);
  707. /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
  708. udelay(10000);
  709. /* Now Read the LM Result Registers */
  710. LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
  711. VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ; /* VDDx100 */
  712. *vdd = VDD;
  713. VDD_diff = VDD - TARGET_VDDx100;
  714. if (VDD_diff < 0)
  715. VDD_diff = -VDD_diff;
  716. if (VDD_diff > VDD_MAX_DIFFx100)
  717. err_mask |= 1;
  718. Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;
  719. codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
  720. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
  721. codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */
  722. udelay(40000);
  723. codsp_write_sop_char(duslic_id, channel,
  724. LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
  725. udelay(40000);
  726. /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
  727. codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
  728. /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
  729. udelay(10000);
  730. /* Now Read the LM Result Registers */
  731. LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
  732. V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/
  733. V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
  734. *v_oh_H = V_out;
  735. Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;
  736. if (Vout_diff < 0)
  737. Vout_diff = -Vout_diff;
  738. if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)
  739. err_mask |= 2;
  740. codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */
  741. udelay(40000);
  742. /* Now Read the LM Result Registers */
  743. LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
  744. V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/
  745. V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
  746. *v_oh_L = V_out;
  747. Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;
  748. if (Vout_diff < 0)
  749. Vout_diff = -Vout_diff;
  750. if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)
  751. err_mask |= 4;
  752. /* perform ring tests */
  753. codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
  754. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
  755. udelay(40000);
  756. codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE);
  757. /* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/
  758. codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);
  759. /* By Default RO1 is selected when ringing RNG-OFFSET = 00 */
  760. /* Now program Hook Threshold while Ring and ac RingTrip to max values */
  761. for(i = 0; i < sizeof(Max_HookRingTh); i++)
  762. codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);
  763. codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
  764. codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
  765. /* select source for the levelmeter to be IO4-IO3 */
  766. codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
  767. udelay(40000);
  768. /* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */
  769. codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);
  770. udelay(10000);
  771. /* Enable LevelMeter to Integrate only once (Rectifier Disabled) */
  772. codsp_write_sop_char(duslic_id, channel,
  773. LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
  774. udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
  775. if (wait_level_metering_finish(duslic_id, channel)) {
  776. udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */
  777. /* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */
  778. Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
  779. Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);
  780. /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
  781. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
  782. /* Now programm Integrator Offset Registers !!! */
  783. codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
  784. codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */
  785. udelay(40000);
  786. /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
  787. codsp_write_sop_char(duslic_id, channel,
  788. LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
  789. udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
  790. /* Poll the LM_OK bit to see when Integration Result is Ready */
  791. if (wait_level_metering_finish(duslic_id, channel)) {
  792. udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
  793. /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
  794. /* ==>After that Result Regs will be updated every 500us !!!) */
  795. LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
  796. V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/
  797. V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
  798. if (V_out < 0)
  799. V_out= -V_out;
  800. if (V_out > MAX_V_RING_MEANx100)
  801. err_mask |= 8;
  802. *ring_mean_v = V_out;
  803. } else {
  804. err_mask |= 8;
  805. *ring_mean_v = 0;
  806. }
  807. } else {
  808. err_mask |= 8;
  809. *ring_mean_v = 0;
  810. }
  811. /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
  812. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
  813. LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
  814. codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
  815. codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
  816. /* Now Enable Rectifier */
  817. /* select source for the levelmeter to be IO4-IO3 */
  818. codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,
  819. LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT);
  820. /* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */
  821. codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);
  822. udelay(40000);
  823. /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
  824. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
  825. LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
  826. udelay(40000);
  827. /* Poll the LM_OK bit to see when Integration Result is Ready */
  828. if (wait_level_metering_finish(duslic_id, channel)) {
  829. udelay(10000);
  830. /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
  831. /* ==>After that Result Regs will be updated every 500us !!!) */
  832. Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
  833. Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
  834. /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
  835. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
  836. /* Now programm Integrator Offset Registers !!! */
  837. codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
  838. /* Be sure that a Ring is generated !!!! */
  839. codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */
  840. udelay(40000);
  841. /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
  842. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
  843. LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
  844. udelay(40000);
  845. /* Poll the LM_OK bit to see when Integration Result is Ready */
  846. if (wait_level_metering_finish(duslic_id, channel)) {
  847. udelay(10000);
  848. /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
  849. /* ==>After that Result Regs will be updated every 500us !!!) */
  850. LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
  851. V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/
  852. V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */
  853. if (V_out < 0)
  854. V_out = -V_out;
  855. Vout_diff = (V_out - TARGET_V_RING_RMSx100);
  856. if (Vout_diff < 0)
  857. Vout_diff = -Vout_diff;
  858. if (Vout_diff > V_RMS_RING_MAX_DIFFx100)
  859. err_mask |= 16;
  860. *ring_rms_v = V_out;
  861. } else {
  862. err_mask |= 16;
  863. *ring_rms_v = 0;
  864. }
  865. } else {
  866. err_mask |= 16;
  867. *ring_rms_v = 0;
  868. }
  869. /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
  870. codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
  871. retrieve_slic_state(slic_id);
  872. return(err_mask);
  873. }
  874. int test_dtmf(int slic_id)
  875. {
  876. unsigned char code;
  877. unsigned char b;
  878. unsigned int intreg;
  879. int duslic_id = slic_id >> 1;
  880. int channel = slic_id & 1;
  881. for (code = 0; code < 16; code++) {
  882. b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
  883. codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
  884. (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
  885. udelay(80000);
  886. intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
  887. if ((intreg & CODSP_INTREG_INT_CH) == 0)
  888. break;
  889. if ((intreg & CODSP_INTREG_DTMF_OK) == 0 ||
  890. codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
  891. break;
  892. b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
  893. codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
  894. b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
  895. udelay(80000);
  896. intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */
  897. }
  898. if (code != 16) {
  899. b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
  900. codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
  901. b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
  902. return(1);
  903. }
  904. return(0);
  905. }
  906. void data_up_persist_time(int duslic_id, int channel, int time_ms)
  907. {
  908. unsigned char b;
  909. b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);
  910. b = (b & 0x0F) | ((time_ms & 0x0F) << 4);
  911. codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);
  912. }
  913. static void program_dtmf_params(int duslic_id, int channel)
  914. {
  915. unsigned char b;
  916. codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);
  917. codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);
  918. codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);
  919. codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);
  920. codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);
  921. codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);
  922. codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);
  923. codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);
  924. codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);
  925. codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);
  926. b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);
  927. codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN);
  928. }
  929. static void codsp_channel_full_reset(int duslic_id, int channel)
  930. {
  931. program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));
  932. program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));
  933. /* program basic configuration registers */
  934. codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);
  935. codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);
  936. codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);
  937. codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);
  938. codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);
  939. codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */
  940. program_dtmf_params(duslic_id, channel);
  941. codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */
  942. data_up_persist_time(duslic_id, channel, 4);
  943. codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */
  944. codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
  945. }
  946. static int codsp_chip_full_reset(int duslic_id)
  947. {
  948. int i, cnt;
  949. int intreg[NUM_CHANNELS];
  950. unsigned char pcm_resync;
  951. unsigned char revision;
  952. codsp_reset_chip(duslic_id);
  953. udelay(2000);
  954. for (i = 0; i < NUM_CHANNELS; i++)
  955. intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);
  956. udelay(1500);
  957. if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {
  958. printf("_HOOK(%d) stayed low\n", duslic_id);
  959. return -1;
  960. }
  961. for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {
  962. if (intreg[i] & CODSP_INTREG_SYNC_FAIL)
  963. pcm_resync |= 1 << i;
  964. }
  965. for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {
  966. for (i = 0; i < NUM_CHANNELS; i++)
  967. codsp_resync_channel(duslic_id, i);
  968. udelay(2000);
  969. pcm_resync = 0;
  970. for (i = 0; i < NUM_CHANNELS; i++) {
  971. if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)
  972. pcm_resync |= 1 << i;
  973. }
  974. }
  975. if (cnt == 5) {
  976. printf("PCM_Resync(%u) not completed\n", duslic_id);
  977. return -2;
  978. }
  979. revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);
  980. printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);
  981. codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */
  982. for (i = 0; i < NUM_CHANNELS; i++) {
  983. codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);
  984. codsp_channel_full_reset(duslic_id, i);
  985. }
  986. return 0;
  987. }
  988. int slic_self_test(int duslic_mask)
  989. {
  990. int slic;
  991. int i;
  992. int r;
  993. long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;
  994. const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };
  995. int error = 0;
  996. for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
  997. if (duslic_mask & (1 << (slic >> 1))) {
  998. r = measure_on_hook_voltages(slic, &vdd,
  999. &v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
  1000. printf("SLIC %u measured voltages (x100):\n\t"
  1001. "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
  1002. slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
  1003. if (r != 0)
  1004. error |= 1 << slic;
  1005. for (i = 0; i < 5; i++)
  1006. if (r & (1 << i))
  1007. printf("\t%s out of range\n", err_txt[i]);
  1008. }
  1009. }
  1010. for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */
  1011. if (duslic_mask & (1 << (slic >> 1))) {
  1012. printf("SLIC %u VOICE PATH...CHECKING", slic);
  1013. printf("\rSLIC %u VOICE PATH...%s\n", slic,
  1014. (r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED ");
  1015. if (r != 0)
  1016. error |= 1 << slic;
  1017. }
  1018. }
  1019. return(error);
  1020. }
  1021. #if defined(CONFIG_NETTA_ISDN)
  1022. #define SPIENS1 (1 << (31 - 15))
  1023. #define SPIENS2 (1 << (31 - 19))
  1024. static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };
  1025. int s_initialized = 0;
  1026. static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)
  1027. {
  1028. unsigned int rx, v;
  1029. _PORTB_SET(spiens_mask_tab[s_id], 0);
  1030. rx = __SPI_Transfer(address);
  1031. switch (address & 0xF0) {
  1032. case 0x60: /* write byte register */
  1033. case 0x70:
  1034. rx = __SPI_Transfer(value);
  1035. break;
  1036. case 0xE0: /* read R6 register */
  1037. v = __SPI_Transfer(0);
  1038. rx = (rx << 8) | v;
  1039. break;
  1040. case 0xF0: /* read byte register */
  1041. rx = __SPI_Transfer(0);
  1042. break;
  1043. }
  1044. _PORTB_SET(spiens_mask_tab[s_id], 1);
  1045. return rx;
  1046. }
  1047. static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
  1048. {
  1049. unsigned int address;
  1050. unsigned int v;
  1051. address = 0x70 | (regno & 15);
  1052. val &= 0xff;
  1053. v = s_transfer_internal(s_id, address, val);
  1054. }
  1055. static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
  1056. {
  1057. unsigned int address;
  1058. unsigned int v;
  1059. address = 0x70 | (regno & 15);
  1060. val &= 0xff;
  1061. v = s_transfer_internal(s_id, address, val);
  1062. }
  1063. static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
  1064. {
  1065. unsigned int address;
  1066. unsigned int v;
  1067. address = (regno & 7) << 4;
  1068. val &= 0xf;
  1069. v = s_transfer_internal(s_id, address | val, 0x00);
  1070. }
  1071. #define BR7_IFR 0x08 /* IDL2 free run */
  1072. #define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */
  1073. #define BR15_OVRL_REG_EN 0x80
  1074. #define OR7_D3VR 0x80 /* disable 3V regulator */
  1075. #define OR8_TEME 0x10 /* TE mode enable */
  1076. #define OR8_MME 0x08 /* master mode enable */
  1077. void s_initialize(void)
  1078. {
  1079. int s_id;
  1080. for (s_id = 0; s_id < 2; s_id++) {
  1081. s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB);
  1082. s_write_BR(s_id, 15, BR15_OVRL_REG_EN);
  1083. s_write_OR(s_id, 8, OR8_TEME | OR8_MME);
  1084. s_write_OR(s_id, 7, OR7_D3VR);
  1085. s_write_OR(s_id, 6, 0);
  1086. s_write_BR(s_id, 15, 0);
  1087. s_write_NR(s_id, 3, 0);
  1088. }
  1089. }
  1090. #endif
  1091. int board_post_codec(int flags)
  1092. {
  1093. int j;
  1094. int r;
  1095. int duslic_mask;
  1096. printf("board_post_dsp\n");
  1097. #if defined(CONFIG_NETTA_ISDN)
  1098. if (s_initialized == 0) {
  1099. s_initialize();
  1100. s_initialized = 1;
  1101. printf("s_initialized\n");
  1102. udelay(20000);
  1103. }
  1104. #endif
  1105. duslic_mask = 0;
  1106. for (j = 0; j < MAX_DUSLIC; j++) {
  1107. if (codsp_chip_full_reset(j) < 0)
  1108. printf("Error initializing DuSLIC#%d\n", j);
  1109. else
  1110. duslic_mask |= 1 << j;
  1111. }
  1112. if (duslic_mask != 0) {
  1113. printf("Testing SLICs...\n");
  1114. r = slic_self_test(duslic_mask);
  1115. for (j = 0; j < MAX_SLICS; j++) {
  1116. if (duslic_mask & (1 << (j >> 1)))
  1117. printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");
  1118. }
  1119. }
  1120. printf("DuSLIC self test finished\n");
  1121. return 0; /* return -1 on error */
  1122. }