imximage.h 4.6 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef _IMXIMAGE_H_
  8. #define _IMXIMAGE_H_
  9. #define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
  10. #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
  11. #define APP_CODE_BARKER 0xB1
  12. #define DCD_BARKER 0xB17219E9
  13. /*
  14. * NOTE: This file must be kept in sync with arch/arm/include/asm/\
  15. * imx-common/imximage.cfg because tools/imximage.c can not
  16. * cross-include headers from arch/arm/ and vice-versa.
  17. */
  18. #define CMD_DATA_STR "DATA"
  19. /* Initial Vector Table Offset */
  20. #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
  21. #define FLASH_OFFSET_STANDARD 0x400
  22. #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
  23. #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
  24. #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
  25. #define FLASH_OFFSET_ONENAND 0x100
  26. #define FLASH_OFFSET_NOR 0x1000
  27. #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
  28. #define FLASH_OFFSET_QSPI 0x1000
  29. /* Initial Load Region Size */
  30. #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
  31. #define FLASH_LOADSIZE_STANDARD 0x1000
  32. #define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
  33. #define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
  34. #define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
  35. #define FLASH_LOADSIZE_ONENAND 0x400
  36. #define FLASH_LOADSIZE_NOR 0x0 /* entire image */
  37. #define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
  38. #define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
  39. /* Command tags and parameters */
  40. #define IVT_HEADER_TAG 0xD1
  41. #define IVT_VERSION 0x40
  42. #define DCD_HEADER_TAG 0xD2
  43. #define DCD_VERSION 0x40
  44. #define DCD_WRITE_DATA_COMMAND_TAG 0xCC
  45. #define DCD_WRITE_DATA_PARAM 0x4
  46. #define DCD_WRITE_CLR_BIT_PARAM 0xC
  47. #define DCD_CHECK_DATA_COMMAND_TAG 0xCF
  48. #define DCD_CHECK_BITS_SET_PARAM 0x14
  49. #define DCD_CHECK_BITS_CLR_PARAM 0x04
  50. enum imximage_cmd {
  51. CMD_INVALID,
  52. CMD_IMAGE_VERSION,
  53. CMD_BOOT_FROM,
  54. CMD_BOOT_OFFSET,
  55. CMD_WRITE_DATA,
  56. CMD_WRITE_CLR_BIT,
  57. CMD_CHECK_BITS_SET,
  58. CMD_CHECK_BITS_CLR,
  59. CMD_CSF,
  60. };
  61. enum imximage_fld_types {
  62. CFG_INVALID = -1,
  63. CFG_COMMAND,
  64. CFG_REG_SIZE,
  65. CFG_REG_ADDRESS,
  66. CFG_REG_VALUE
  67. };
  68. enum imximage_version {
  69. IMXIMAGE_VER_INVALID = -1,
  70. IMXIMAGE_V1 = 1,
  71. IMXIMAGE_V2
  72. };
  73. typedef struct {
  74. uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
  75. uint32_t addr; /* Address to write to */
  76. uint32_t value; /* Data to write */
  77. } dcd_type_addr_data_t;
  78. typedef struct {
  79. uint32_t barker; /* Barker for sanity check */
  80. uint32_t length; /* Device configuration length (without preamble) */
  81. } dcd_preamble_t;
  82. typedef struct {
  83. dcd_preamble_t preamble;
  84. dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
  85. } dcd_v1_t;
  86. typedef struct {
  87. uint32_t app_code_jump_vector;
  88. uint32_t app_code_barker;
  89. uint32_t app_code_csf;
  90. uint32_t dcd_ptr_ptr;
  91. uint32_t super_root_key;
  92. uint32_t dcd_ptr;
  93. uint32_t app_dest_ptr;
  94. } flash_header_v1_t;
  95. typedef struct {
  96. uint32_t length; /* Length of data to be read from flash */
  97. } flash_cfg_parms_t;
  98. typedef struct {
  99. flash_header_v1_t fhdr;
  100. dcd_v1_t dcd_table;
  101. flash_cfg_parms_t ext_header;
  102. } imx_header_v1_t;
  103. typedef struct {
  104. uint32_t addr;
  105. uint32_t value;
  106. } dcd_addr_data_t;
  107. typedef struct {
  108. uint8_t tag;
  109. uint16_t length;
  110. uint8_t version;
  111. } __attribute__((packed)) ivt_header_t;
  112. typedef struct {
  113. uint8_t tag;
  114. uint16_t length;
  115. uint8_t param;
  116. } __attribute__((packed)) write_dcd_command_t;
  117. struct dcd_v2_cmd {
  118. write_dcd_command_t write_dcd_command;
  119. dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
  120. };
  121. typedef struct {
  122. ivt_header_t header;
  123. struct dcd_v2_cmd dcd_cmd;
  124. uint32_t padding[1]; /* end up on an 8-byte boundary */
  125. } dcd_v2_t;
  126. typedef struct {
  127. uint32_t start;
  128. uint32_t size;
  129. uint32_t plugin;
  130. } boot_data_t;
  131. typedef struct {
  132. ivt_header_t header;
  133. uint32_t entry;
  134. uint32_t reserved1;
  135. uint32_t dcd_ptr;
  136. uint32_t boot_data_ptr;
  137. uint32_t self;
  138. uint32_t csf;
  139. uint32_t reserved2;
  140. } flash_header_v2_t;
  141. typedef struct {
  142. flash_header_v2_t fhdr;
  143. boot_data_t boot_data;
  144. dcd_v2_t dcd_table;
  145. } imx_header_v2_t;
  146. /* The header must be aligned to 4k on MX53 for NAND boot */
  147. struct imx_header {
  148. union {
  149. imx_header_v1_t hdr_v1;
  150. imx_header_v2_t hdr_v2;
  151. } header;
  152. };
  153. typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
  154. char *name, int lineno,
  155. int fld, uint32_t value,
  156. uint32_t off);
  157. typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len,
  158. int32_t cmd);
  159. typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
  160. uint32_t dcd_len,
  161. char *name, int lineno);
  162. typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
  163. uint32_t entry_point, uint32_t flash_offset);
  164. #endif /* _IMXIMAGE_H_ */