pci.c 18 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * (C) Copyright 2002
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. /*
  12. * PCI routines
  13. */
  14. #include <common.h>
  15. #include <bootretry.h>
  16. #include <cli.h>
  17. #include <command.h>
  18. #include <console.h>
  19. #include <dm.h>
  20. #include <asm/processor.h>
  21. #include <asm/io.h>
  22. #include <pci.h>
  23. struct pci_reg_info {
  24. const char *name;
  25. enum pci_size_t size;
  26. u8 offset;
  27. };
  28. static int pci_byte_size(enum pci_size_t size)
  29. {
  30. switch (size) {
  31. case PCI_SIZE_8:
  32. return 1;
  33. case PCI_SIZE_16:
  34. return 2;
  35. case PCI_SIZE_32:
  36. default:
  37. return 4;
  38. }
  39. }
  40. static int pci_field_width(enum pci_size_t size)
  41. {
  42. return pci_byte_size(size) * 2;
  43. }
  44. #ifdef CONFIG_DM_PCI
  45. static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
  46. {
  47. for (; regs->name; regs++) {
  48. unsigned long val;
  49. dm_pci_read_config(dev, regs->offset, &val, regs->size);
  50. printf(" %s =%*s%#.*lx\n", regs->name,
  51. (int)(28 - strlen(regs->name)), "",
  52. pci_field_width(regs->size), val);
  53. }
  54. }
  55. #else
  56. static unsigned long pci_read_config(pci_dev_t dev, int offset,
  57. enum pci_size_t size)
  58. {
  59. u32 val32;
  60. u16 val16;
  61. u8 val8;
  62. switch (size) {
  63. case PCI_SIZE_8:
  64. pci_read_config_byte(dev, offset, &val8);
  65. return val8;
  66. case PCI_SIZE_16:
  67. pci_read_config_word(dev, offset, &val16);
  68. return val16;
  69. case PCI_SIZE_32:
  70. default:
  71. pci_read_config_dword(dev, offset, &val32);
  72. return val32;
  73. }
  74. }
  75. static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
  76. {
  77. for (; regs->name; regs++) {
  78. printf(" %s =%*s%#.*lx\n", regs->name,
  79. (int)(28 - strlen(regs->name)), "",
  80. pci_field_width(regs->size),
  81. pci_read_config(dev, regs->offset, regs->size));
  82. }
  83. }
  84. #endif
  85. static struct pci_reg_info regs_start[] = {
  86. { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
  87. { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
  88. { "command register ID", PCI_SIZE_16, PCI_COMMAND },
  89. { "status register", PCI_SIZE_16, PCI_STATUS },
  90. { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
  91. {},
  92. };
  93. static struct pci_reg_info regs_rest[] = {
  94. { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
  95. { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
  96. { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
  97. { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
  98. { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
  99. { "BIST", PCI_SIZE_8, PCI_BIST },
  100. { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
  101. {},
  102. };
  103. static struct pci_reg_info regs_normal[] = {
  104. { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
  105. { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
  106. { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
  107. { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
  108. { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
  109. { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
  110. { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
  111. { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
  112. { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
  113. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  114. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  115. { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
  116. { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
  117. {},
  118. };
  119. static struct pci_reg_info regs_bridge[] = {
  120. { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
  121. { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
  122. { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
  123. { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
  124. { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
  125. { "IO base", PCI_SIZE_8, PCI_IO_BASE },
  126. { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
  127. { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
  128. { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
  129. { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
  130. { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
  131. { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
  132. { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
  133. { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
  134. { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
  135. { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
  136. { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
  137. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  138. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  139. { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
  140. {},
  141. };
  142. static struct pci_reg_info regs_cardbus[] = {
  143. { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
  144. { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
  145. { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
  146. { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
  147. { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
  148. { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
  149. { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
  150. { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
  151. { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
  152. { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
  153. { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
  154. { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
  155. { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
  156. { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
  157. { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
  158. { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
  159. { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
  160. { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
  161. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  162. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  163. { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
  164. { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
  165. { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
  166. { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
  167. {},
  168. };
  169. /**
  170. * pci_header_show() - Show the header of the specified PCI device.
  171. *
  172. * @dev: Bus+Device+Function number
  173. */
  174. #ifdef CONFIG_DM_PCI
  175. void pci_header_show(struct udevice *dev)
  176. #else
  177. void pci_header_show(pci_dev_t dev)
  178. #endif
  179. {
  180. #ifdef CONFIG_DM_PCI
  181. unsigned long class, header_type;
  182. dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
  183. dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
  184. #else
  185. u8 class, header_type;
  186. pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
  187. pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
  188. #endif
  189. pci_show_regs(dev, regs_start);
  190. printf(" class code = 0x%.2x (%s)\n", (int)class,
  191. pci_class_str(class));
  192. pci_show_regs(dev, regs_rest);
  193. switch (header_type & 0x03) {
  194. case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
  195. pci_show_regs(dev, regs_normal);
  196. break;
  197. case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
  198. pci_show_regs(dev, regs_bridge);
  199. break;
  200. case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
  201. pci_show_regs(dev, regs_cardbus);
  202. break;
  203. default:
  204. printf("unknown header\n");
  205. break;
  206. }
  207. }
  208. void pciinfo_header(int busnum, bool short_listing)
  209. {
  210. printf("Scanning PCI devices on bus %d\n", busnum);
  211. if (short_listing) {
  212. printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
  213. printf("_____________________________________________________________\n");
  214. }
  215. }
  216. #ifdef CONFIG_DM_PCI
  217. /**
  218. * pci_header_show_brief() - Show the short-form PCI device header
  219. *
  220. * Reads and prints the header of the specified PCI device in short form.
  221. *
  222. * @dev: PCI device to show
  223. */
  224. static void pci_header_show_brief(struct udevice *dev)
  225. {
  226. ulong vendor, device;
  227. ulong class, subclass;
  228. dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
  229. dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
  230. dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
  231. dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
  232. printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
  233. vendor, device,
  234. pci_class_str(class), subclass);
  235. }
  236. static void pciinfo(struct udevice *bus, bool short_listing)
  237. {
  238. struct udevice *dev;
  239. pciinfo_header(bus->seq, short_listing);
  240. for (device_find_first_child(bus, &dev);
  241. dev;
  242. device_find_next_child(&dev)) {
  243. struct pci_child_platdata *pplat;
  244. pplat = dev_get_parent_platdata(dev);
  245. if (short_listing) {
  246. printf("%02x.%02x.%02x ", bus->seq,
  247. PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
  248. pci_header_show_brief(dev);
  249. } else {
  250. printf("\nFound PCI device %02x.%02x.%02x:\n", bus->seq,
  251. PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
  252. pci_header_show(dev);
  253. }
  254. }
  255. }
  256. #else
  257. /**
  258. * pci_header_show_brief() - Show the short-form PCI device header
  259. *
  260. * Reads and prints the header of the specified PCI device in short form.
  261. *
  262. * @dev: Bus+Device+Function number
  263. */
  264. void pci_header_show_brief(pci_dev_t dev)
  265. {
  266. u16 vendor, device;
  267. u8 class, subclass;
  268. pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
  269. pci_read_config_word(dev, PCI_DEVICE_ID, &device);
  270. pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
  271. pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
  272. printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
  273. vendor, device,
  274. pci_class_str(class), subclass);
  275. }
  276. /**
  277. * pciinfo() - Show a list of devices on the PCI bus
  278. *
  279. * Show information about devices on PCI bus. Depending on @short_pci_listing
  280. * the output will be more or less exhaustive.
  281. *
  282. * @bus_num: The number of the bus to be scanned
  283. * @short_pci_listing: true to use short form, showing only a brief header
  284. * for each device
  285. */
  286. void pciinfo(int bus_num, int short_pci_listing)
  287. {
  288. struct pci_controller *hose = pci_bus_to_hose(bus_num);
  289. int device;
  290. int function;
  291. unsigned char header_type;
  292. unsigned short vendor_id;
  293. pci_dev_t dev;
  294. int ret;
  295. if (!hose)
  296. return;
  297. pciinfo_header(bus_num, short_pci_listing);
  298. for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
  299. header_type = 0;
  300. vendor_id = 0;
  301. for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
  302. function++) {
  303. /*
  304. * If this is not a multi-function device, we skip
  305. * the rest.
  306. */
  307. if (function && !(header_type & 0x80))
  308. break;
  309. dev = PCI_BDF(bus_num, device, function);
  310. if (pci_skip_dev(hose, dev))
  311. continue;
  312. ret = pci_read_config_word(dev, PCI_VENDOR_ID,
  313. &vendor_id);
  314. if (ret)
  315. goto error;
  316. if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
  317. continue;
  318. if (!function) {
  319. pci_read_config_byte(dev, PCI_HEADER_TYPE,
  320. &header_type);
  321. }
  322. if (short_pci_listing) {
  323. printf("%02x.%02x.%02x ", bus_num, device,
  324. function);
  325. pci_header_show_brief(dev);
  326. } else {
  327. printf("\nFound PCI device %02x.%02x.%02x:\n",
  328. bus_num, device, function);
  329. pci_header_show(dev);
  330. }
  331. }
  332. }
  333. return;
  334. error:
  335. printf("Cannot read bus configuration: %d\n", ret);
  336. }
  337. #endif
  338. /**
  339. * get_pci_dev() - Convert the "bus.device.function" identifier into a number
  340. *
  341. * @name: Device string in the form "bus.device.function" where each is in hex
  342. * @return encoded pci_dev_t or -1 if the string was invalid
  343. */
  344. static pci_dev_t get_pci_dev(char *name)
  345. {
  346. char cnum[12];
  347. int len, i, iold, n;
  348. int bdfs[3] = {0,0,0};
  349. len = strlen(name);
  350. if (len > 8)
  351. return -1;
  352. for (i = 0, iold = 0, n = 0; i < len; i++) {
  353. if (name[i] == '.') {
  354. memcpy(cnum, &name[iold], i - iold);
  355. cnum[i - iold] = '\0';
  356. bdfs[n++] = simple_strtoul(cnum, NULL, 16);
  357. iold = i + 1;
  358. }
  359. }
  360. strcpy(cnum, &name[iold]);
  361. if (n == 0)
  362. n = 1;
  363. bdfs[n] = simple_strtoul(cnum, NULL, 16);
  364. return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
  365. }
  366. #ifdef CONFIG_DM_PCI
  367. static int pci_cfg_display(struct udevice *dev, ulong addr,
  368. enum pci_size_t size, ulong length)
  369. #else
  370. static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
  371. ulong length)
  372. #endif
  373. {
  374. #define DISP_LINE_LEN 16
  375. ulong i, nbytes, linebytes;
  376. int byte_size;
  377. int rc = 0;
  378. byte_size = pci_byte_size(size);
  379. if (length == 0)
  380. length = 0x40 / byte_size; /* Standard PCI config space */
  381. /* Print the lines.
  382. * once, and all accesses are with the specified bus width.
  383. */
  384. nbytes = length * byte_size;
  385. do {
  386. printf("%08lx:", addr);
  387. linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
  388. for (i = 0; i < linebytes; i += byte_size) {
  389. unsigned long val;
  390. #ifdef CONFIG_DM_PCI
  391. dm_pci_read_config(dev, addr, &val, size);
  392. #else
  393. val = pci_read_config(bdf, addr, size);
  394. #endif
  395. printf(" %0*lx", pci_field_width(size), val);
  396. addr += byte_size;
  397. }
  398. printf("\n");
  399. nbytes -= linebytes;
  400. if (ctrlc()) {
  401. rc = 1;
  402. break;
  403. }
  404. } while (nbytes > 0);
  405. return (rc);
  406. }
  407. #ifndef CONFIG_DM_PCI
  408. static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
  409. {
  410. if (size == 4) {
  411. pci_write_config_dword(bdf, addr, value);
  412. }
  413. else if (size == 2) {
  414. ushort val = value & 0xffff;
  415. pci_write_config_word(bdf, addr, val);
  416. }
  417. else {
  418. u_char val = value & 0xff;
  419. pci_write_config_byte(bdf, addr, val);
  420. }
  421. return 0;
  422. }
  423. #endif
  424. #ifdef CONFIG_DM_PCI
  425. static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
  426. ulong value, int incrflag)
  427. #else
  428. static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
  429. int incrflag)
  430. #endif
  431. {
  432. ulong i;
  433. int nbytes;
  434. ulong val;
  435. /* Print the address, followed by value. Then accept input for
  436. * the next value. A non-converted value exits.
  437. */
  438. do {
  439. printf("%08lx:", addr);
  440. #ifdef CONFIG_DM_PCI
  441. dm_pci_read_config(dev, addr, &val, size);
  442. #else
  443. val = pci_read_config(bdf, addr, size);
  444. #endif
  445. printf(" %0*lx", pci_field_width(size), val);
  446. nbytes = cli_readline(" ? ");
  447. if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
  448. /* <CR> pressed as only input, don't modify current
  449. * location and move to next. "-" pressed will go back.
  450. */
  451. if (incrflag)
  452. addr += nbytes ? -size : size;
  453. nbytes = 1;
  454. /* good enough to not time out */
  455. bootretry_reset_cmd_timeout();
  456. }
  457. #ifdef CONFIG_BOOT_RETRY_TIME
  458. else if (nbytes == -2) {
  459. break; /* timed out, exit the command */
  460. }
  461. #endif
  462. else {
  463. char *endp;
  464. i = simple_strtoul(console_buffer, &endp, 16);
  465. nbytes = endp - console_buffer;
  466. if (nbytes) {
  467. /* good enough to not time out
  468. */
  469. bootretry_reset_cmd_timeout();
  470. #ifdef CONFIG_DM_PCI
  471. dm_pci_write_config(dev, addr, i, size);
  472. #else
  473. pci_cfg_write(bdf, addr, size, i);
  474. #endif
  475. if (incrflag)
  476. addr += size;
  477. }
  478. }
  479. } while (nbytes);
  480. return 0;
  481. }
  482. /* PCI Configuration Space access commands
  483. *
  484. * Syntax:
  485. * pci display[.b, .w, .l] bus.device.function} [addr] [len]
  486. * pci next[.b, .w, .l] bus.device.function [addr]
  487. * pci modify[.b, .w, .l] bus.device.function [addr]
  488. * pci write[.b, .w, .l] bus.device.function addr value
  489. */
  490. static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  491. {
  492. ulong addr = 0, value = 0, cmd_size = 0;
  493. enum pci_size_t size = PCI_SIZE_32;
  494. #ifdef CONFIG_DM_PCI
  495. struct udevice *dev, *bus;
  496. #else
  497. pci_dev_t dev;
  498. #endif
  499. int busnum = 0;
  500. pci_dev_t bdf = 0;
  501. char cmd = 's';
  502. int ret = 0;
  503. if (argc > 1)
  504. cmd = argv[1][0];
  505. switch (cmd) {
  506. case 'd': /* display */
  507. case 'n': /* next */
  508. case 'm': /* modify */
  509. case 'w': /* write */
  510. /* Check for a size specification. */
  511. cmd_size = cmd_get_data_size(argv[1], 4);
  512. size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
  513. if (argc > 3)
  514. addr = simple_strtoul(argv[3], NULL, 16);
  515. if (argc > 4)
  516. value = simple_strtoul(argv[4], NULL, 16);
  517. case 'h': /* header */
  518. if (argc < 3)
  519. goto usage;
  520. if ((bdf = get_pci_dev(argv[2])) == -1)
  521. return 1;
  522. break;
  523. #if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI)
  524. case 'e':
  525. pci_init();
  526. return 0;
  527. #endif
  528. default: /* scan bus */
  529. value = 1; /* short listing */
  530. if (argc > 1) {
  531. if (argv[argc-1][0] == 'l') {
  532. value = 0;
  533. argc--;
  534. }
  535. if (argc > 1)
  536. busnum = simple_strtoul(argv[1], NULL, 16);
  537. }
  538. #ifdef CONFIG_DM_PCI
  539. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
  540. if (ret) {
  541. printf("No such bus\n");
  542. return CMD_RET_FAILURE;
  543. }
  544. pciinfo(bus, value);
  545. #else
  546. pciinfo(busnum, value);
  547. #endif
  548. return 0;
  549. }
  550. #ifdef CONFIG_DM_PCI
  551. ret = dm_pci_bus_find_bdf(bdf, &dev);
  552. if (ret) {
  553. printf("No such device\n");
  554. return CMD_RET_FAILURE;
  555. }
  556. #else
  557. dev = bdf;
  558. #endif
  559. switch (argv[1][0]) {
  560. case 'h': /* header */
  561. pci_header_show(dev);
  562. break;
  563. case 'd': /* display */
  564. return pci_cfg_display(dev, addr, size, value);
  565. case 'n': /* next */
  566. if (argc < 4)
  567. goto usage;
  568. ret = pci_cfg_modify(dev, addr, size, value, 0);
  569. break;
  570. case 'm': /* modify */
  571. if (argc < 4)
  572. goto usage;
  573. ret = pci_cfg_modify(dev, addr, size, value, 1);
  574. break;
  575. case 'w': /* write */
  576. if (argc < 5)
  577. goto usage;
  578. #ifdef CONFIG_DM_PCI
  579. ret = dm_pci_write_config(dev, addr, value, size);
  580. #else
  581. ret = pci_cfg_write(dev, addr, size, value);
  582. #endif
  583. break;
  584. default:
  585. ret = CMD_RET_USAGE;
  586. break;
  587. }
  588. return ret;
  589. usage:
  590. return CMD_RET_USAGE;
  591. }
  592. /***************************************************/
  593. #ifdef CONFIG_SYS_LONGHELP
  594. static char pci_help_text[] =
  595. "[bus] [long]\n"
  596. " - short or long list of PCI devices on bus 'bus'\n"
  597. #if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI)
  598. "pci enum\n"
  599. " - Enumerate PCI buses\n"
  600. #endif
  601. "pci header b.d.f\n"
  602. " - show header of PCI device 'bus.device.function'\n"
  603. "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
  604. " - display PCI configuration space (CFG)\n"
  605. "pci next[.b, .w, .l] b.d.f address\n"
  606. " - modify, read and keep CFG address\n"
  607. "pci modify[.b, .w, .l] b.d.f address\n"
  608. " - modify, auto increment CFG address\n"
  609. "pci write[.b, .w, .l] b.d.f address value\n"
  610. " - write to CFG address";
  611. #endif
  612. U_BOOT_CMD(
  613. pci, 5, 1, do_pci,
  614. "list and access PCI Configuration Space", pci_help_text
  615. );