imx6qdl-gw5913.dtsi 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. nand = &gpmi;
  14. usb0 = &usbh1;
  15. usb1 = &usbotg;
  16. };
  17. chosen {
  18. stdout-path = &uart2;
  19. };
  20. gpio-keys {
  21. compatible = "gpio-keys";
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. user-pb {
  25. label = "user_pb";
  26. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  27. linux,code = <BTN_0>;
  28. };
  29. user-pb1x {
  30. label = "user_pb1x";
  31. linux,code = <BTN_1>;
  32. interrupt-parent = <&gsc>;
  33. interrupts = <0>;
  34. };
  35. key-erased {
  36. label = "key-erased";
  37. linux,code = <BTN_2>;
  38. interrupt-parent = <&gsc>;
  39. interrupts = <1>;
  40. };
  41. eeprom-wp {
  42. label = "eeprom_wp";
  43. linux,code = <BTN_3>;
  44. interrupt-parent = <&gsc>;
  45. interrupts = <2>;
  46. };
  47. tamper {
  48. label = "tamper";
  49. linux,code = <BTN_4>;
  50. interrupt-parent = <&gsc>;
  51. interrupts = <5>;
  52. };
  53. switch-hold {
  54. label = "switch_hold";
  55. linux,code = <BTN_5>;
  56. interrupt-parent = <&gsc>;
  57. interrupts = <7>;
  58. };
  59. };
  60. leds {
  61. compatible = "gpio-leds";
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&pinctrl_gpio_leds>;
  64. led0: user1 {
  65. label = "user1";
  66. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  67. default-state = "on";
  68. linux,default-trigger = "heartbeat";
  69. };
  70. led1: user2 {
  71. label = "user2";
  72. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  73. default-state = "off";
  74. };
  75. };
  76. memory@10000000 {
  77. device_type = "memory";
  78. reg = <0x10000000 0x20000000>;
  79. };
  80. pps {
  81. compatible = "pps-gpio";
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&pinctrl_pps>;
  84. gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
  85. status = "okay";
  86. };
  87. reg_3p3v: regulator-3p3v {
  88. compatible = "regulator-fixed";
  89. regulator-name = "3P3V";
  90. regulator-min-microvolt = <3300000>;
  91. regulator-max-microvolt = <3300000>;
  92. regulator-always-on;
  93. };
  94. reg_5p0v: regulator-5p0v {
  95. compatible = "regulator-fixed";
  96. regulator-name = "5P0V";
  97. regulator-min-microvolt = <5000000>;
  98. regulator-max-microvolt = <5000000>;
  99. regulator-always-on;
  100. };
  101. };
  102. &fec {
  103. pinctrl-names = "default";
  104. pinctrl-0 = <&pinctrl_enet>;
  105. phy-mode = "rgmii-id";
  106. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  107. phy-reset-duration = <10>;
  108. phy-reset-post-delay = <100>;
  109. status = "okay";
  110. };
  111. &gpmi {
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&pinctrl_gpmi_nand>;
  114. status = "okay";
  115. };
  116. &i2c1 {
  117. clock-frequency = <100000>;
  118. pinctrl-names = "default";
  119. pinctrl-0 = <&pinctrl_i2c1>;
  120. status = "okay";
  121. gsc: gsc@20 {
  122. compatible = "gw,gsc";
  123. reg = <0x20>;
  124. interrupt-parent = <&gpio1>;
  125. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  126. interrupt-controller;
  127. #interrupt-cells = <1>;
  128. #size-cells = <0>;
  129. adc {
  130. compatible = "gw,gsc-adc";
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. channel@6 {
  134. gw,mode = <0>;
  135. reg = <0x06>;
  136. label = "temp";
  137. };
  138. channel@8 {
  139. gw,mode = <3>;
  140. reg = <0x08>;
  141. label = "vdd_bat";
  142. };
  143. channel@82 {
  144. gw,mode = <2>;
  145. reg = <0x82>;
  146. label = "vdd_vin";
  147. gw,voltage-divider-ohms = <22100 1000>;
  148. gw,voltage-offset-microvolt = <800000>;
  149. };
  150. channel@84 {
  151. gw,mode = <2>;
  152. reg = <0x84>;
  153. label = "vdd_5p0";
  154. gw,voltage-divider-ohms = <22100 10000>;
  155. };
  156. channel@86 {
  157. gw,mode = <2>;
  158. reg = <0x86>;
  159. label = "vdd_3p3";
  160. gw,voltage-divider-ohms = <10000 10000>;
  161. };
  162. channel@88 {
  163. gw,mode = <2>;
  164. reg = <0x88>;
  165. label = "vdd_2p5";
  166. gw,voltage-divider-ohms = <10000 10000>;
  167. };
  168. channel@8c {
  169. gw,mode = <2>;
  170. reg = <0x8c>;
  171. label = "vdd_arm";
  172. };
  173. channel@8e {
  174. gw,mode = <2>;
  175. reg = <0x8e>;
  176. label = "vdd_soc";
  177. };
  178. channel@90 {
  179. gw,mode = <2>;
  180. reg = <0x90>;
  181. label = "vdd_1p5";
  182. };
  183. channel@92 {
  184. gw,mode = <2>;
  185. reg = <0x92>;
  186. label = "vdd_1p0";
  187. };
  188. channel@98 {
  189. gw,mode = <2>;
  190. reg = <0x98>;
  191. label = "vdd_3p0";
  192. };
  193. channel@9a {
  194. gw,mode = <2>;
  195. reg = <0x9a>;
  196. label = "vdd_an1";
  197. gw,voltage-divider-ohms = <10000 10000>;
  198. };
  199. channel@a2 {
  200. gw,mode = <2>;
  201. reg = <0xa2>;
  202. label = "vdd_gsc";
  203. gw,voltage-divider-ohms = <10000 10000>;
  204. };
  205. };
  206. };
  207. gsc_gpio: gpio@23 {
  208. compatible = "nxp,pca9555";
  209. reg = <0x23>;
  210. gpio-controller;
  211. #gpio-cells = <2>;
  212. interrupt-parent = <&gsc>;
  213. interrupts = <4>;
  214. };
  215. eeprom@50 {
  216. compatible = "atmel,24c02";
  217. reg = <0x50>;
  218. pagesize = <16>;
  219. };
  220. eeprom@51 {
  221. compatible = "atmel,24c02";
  222. reg = <0x51>;
  223. pagesize = <16>;
  224. };
  225. eeprom@52 {
  226. compatible = "atmel,24c02";
  227. reg = <0x52>;
  228. pagesize = <16>;
  229. };
  230. eeprom@53 {
  231. compatible = "atmel,24c02";
  232. reg = <0x53>;
  233. pagesize = <16>;
  234. };
  235. rtc@68 {
  236. compatible = "dallas,ds1672";
  237. reg = <0x68>;
  238. };
  239. };
  240. &i2c2 {
  241. clock-frequency = <100000>;
  242. pinctrl-names = "default";
  243. pinctrl-0 = <&pinctrl_i2c2>;
  244. status = "okay";
  245. };
  246. &i2c3 {
  247. clock-frequency = <100000>;
  248. pinctrl-names = "default";
  249. pinctrl-0 = <&pinctrl_i2c3>;
  250. status = "okay";
  251. };
  252. &pcie {
  253. pinctrl-names = "default";
  254. pinctrl-0 = <&pinctrl_pcie>;
  255. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  256. status = "okay";
  257. };
  258. &pwm2 {
  259. pinctrl-names = "default";
  260. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  261. status = "disabled";
  262. };
  263. &pwm3 {
  264. pinctrl-names = "default";
  265. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  266. status = "disabled";
  267. };
  268. &pwm4 {
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  271. status = "disabled";
  272. };
  273. &uart1 {
  274. pinctrl-names = "default";
  275. pinctrl-0 = <&pinctrl_uart1>;
  276. status = "okay";
  277. };
  278. &uart2 {
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&pinctrl_uart2>;
  281. status = "okay";
  282. };
  283. &uart3 {
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&pinctrl_uart3>;
  286. status = "okay";
  287. };
  288. &uart5 {
  289. pinctrl-names = "default";
  290. pinctrl-0 = <&pinctrl_uart5>;
  291. status = "okay";
  292. };
  293. &usbotg {
  294. pinctrl-names = "default";
  295. pinctrl-0 = <&pinctrl_usbotg>;
  296. disable-over-current;
  297. dr_mode = "host";
  298. status = "okay";
  299. };
  300. &usbh1 {
  301. status = "okay";
  302. };
  303. &wdog1 {
  304. pinctrl-names = "default";
  305. pinctrl-0 = <&pinctrl_wdog>;
  306. fsl,ext-reset-output;
  307. };
  308. &iomuxc {
  309. pinctrl_enet: enetgrp {
  310. fsl,pins = <
  311. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  312. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  313. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  314. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  315. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  316. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  317. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  318. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  319. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  320. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  321. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  322. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  323. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  324. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  325. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  326. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  327. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  328. >;
  329. };
  330. pinctrl_gpio_leds: gpioledsgrp {
  331. fsl,pins = <
  332. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  333. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  334. >;
  335. };
  336. pinctrl_gpmi_nand: gpminandgrp {
  337. fsl,pins = <
  338. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  339. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  340. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  341. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  342. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  343. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  344. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  345. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  346. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  347. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  348. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  349. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  350. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  351. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  352. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  353. >;
  354. };
  355. pinctrl_i2c1: i2c1grp {
  356. fsl,pins = <
  357. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  358. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  359. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
  360. >;
  361. };
  362. pinctrl_i2c2: i2c2grp {
  363. fsl,pins = <
  364. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  365. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  366. >;
  367. };
  368. pinctrl_i2c3: i2c3grp {
  369. fsl,pins = <
  370. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  371. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  372. >;
  373. };
  374. pinctrl_pcie: pciegrp {
  375. fsl,pins = <
  376. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
  377. >;
  378. };
  379. pinctrl_pps: ppsgrp {
  380. fsl,pins = <
  381. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1
  382. >;
  383. };
  384. pinctrl_pwm2: pwm2grp {
  385. fsl,pins = <
  386. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  387. >;
  388. };
  389. pinctrl_pwm3: pwm3grp {
  390. fsl,pins = <
  391. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  392. >;
  393. };
  394. pinctrl_pwm4: pwm4grp {
  395. fsl,pins = <
  396. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  397. >;
  398. };
  399. pinctrl_uart1: uart1grp {
  400. fsl,pins = <
  401. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  402. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  403. >;
  404. };
  405. pinctrl_uart2: uart2grp {
  406. fsl,pins = <
  407. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  408. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  409. >;
  410. };
  411. pinctrl_uart3: uart3grp {
  412. fsl,pins = <
  413. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  414. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  415. >;
  416. };
  417. pinctrl_uart5: uart5grp {
  418. fsl,pins = <
  419. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  420. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  421. >;
  422. };
  423. pinctrl_usbotg: usbotggrp {
  424. fsl,pins = <
  425. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  426. >;
  427. };
  428. pinctrl_wdog: wdoggrp {
  429. fsl,pins = <
  430. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  431. >;
  432. };
  433. };