imx6qdl-gw5910.dtsi 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. mmc0 = &usdhc3;
  15. };
  16. chosen {
  17. stdout-path = &uart2;
  18. };
  19. memory@10000000 {
  20. device_type = "memory";
  21. reg = <0x10000000 0x20000000>;
  22. };
  23. gpio-keys {
  24. compatible = "gpio-keys";
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. user-pb {
  28. label = "user_pb";
  29. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  30. linux,code = <BTN_0>;
  31. };
  32. user-pb1x {
  33. label = "user_pb1x";
  34. linux,code = <BTN_1>;
  35. interrupt-parent = <&gsc>;
  36. interrupts = <0>;
  37. };
  38. key-erased {
  39. label = "key-erased";
  40. linux,code = <BTN_2>;
  41. interrupt-parent = <&gsc>;
  42. interrupts = <1>;
  43. };
  44. eeprom-wp {
  45. label = "eeprom_wp";
  46. linux,code = <BTN_3>;
  47. interrupt-parent = <&gsc>;
  48. interrupts = <2>;
  49. };
  50. tamper {
  51. label = "tamper";
  52. linux,code = <BTN_4>;
  53. interrupt-parent = <&gsc>;
  54. interrupts = <5>;
  55. };
  56. switch-hold {
  57. label = "switch_hold";
  58. linux,code = <BTN_5>;
  59. interrupt-parent = <&gsc>;
  60. interrupts = <7>;
  61. };
  62. };
  63. leds {
  64. compatible = "gpio-leds";
  65. pinctrl-names = "default";
  66. pinctrl-0 = <&pinctrl_gpio_leds>;
  67. led0: user1 {
  68. label = "user1";
  69. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  70. default-state = "on";
  71. linux,default-trigger = "heartbeat";
  72. };
  73. led1: user2 {
  74. label = "user2";
  75. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  76. default-state = "off";
  77. };
  78. led2: user3 {
  79. label = "user3";
  80. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  81. default-state = "off";
  82. };
  83. };
  84. pps {
  85. compatible = "pps-gpio";
  86. pinctrl-names = "default";
  87. pinctrl-0 = <&pinctrl_pps>;
  88. gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  89. status = "okay";
  90. };
  91. reg_3p3v: regulator-3p3v {
  92. compatible = "regulator-fixed";
  93. regulator-name = "3P3V";
  94. regulator-min-microvolt = <3300000>;
  95. regulator-max-microvolt = <3300000>;
  96. regulator-always-on;
  97. };
  98. reg_5p0v: regulator-5p0v {
  99. compatible = "regulator-fixed";
  100. regulator-name = "5P0V";
  101. regulator-min-microvolt = <5000000>;
  102. regulator-max-microvolt = <5000000>;
  103. regulator-always-on;
  104. };
  105. reg_wl: regulator-wl {
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&pinctrl_reg_wl>;
  108. compatible = "regulator-fixed";
  109. regulator-name = "wl";
  110. gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  111. startup-delay-us = <100>;
  112. enable-active-high;
  113. regulator-min-microvolt = <3300000>;
  114. regulator-max-microvolt = <3300000>;
  115. };
  116. };
  117. &ecspi3 {
  118. cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  119. pinctrl-names = "default";
  120. pinctrl-0 = <&pinctrl_ecspi3>;
  121. status = "okay";
  122. };
  123. &fec {
  124. pinctrl-names = "default";
  125. pinctrl-0 = <&pinctrl_enet>;
  126. phy-mode = "rgmii-id";
  127. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  128. phy-reset-duration = <10>;
  129. phy-reset-post-delay = <100>;
  130. status = "okay";
  131. };
  132. &gpmi {
  133. pinctrl-names = "default";
  134. pinctrl-0 = <&pinctrl_gpmi_nand>;
  135. status = "okay";
  136. };
  137. &i2c1 {
  138. clock-frequency = <100000>;
  139. pinctrl-names = "default";
  140. pinctrl-0 = <&pinctrl_i2c1>;
  141. status = "okay";
  142. gsc: gsc@20 {
  143. compatible = "gw,gsc";
  144. reg = <0x20>;
  145. interrupt-parent = <&gpio1>;
  146. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  147. interrupt-controller;
  148. #interrupt-cells = <1>;
  149. #size-cells = <0>;
  150. adc {
  151. compatible = "gw,gsc-adc";
  152. #address-cells = <1>;
  153. #size-cells = <0>;
  154. channel@6 {
  155. gw,mode = <0>;
  156. reg = <0x06>;
  157. label = "temp";
  158. };
  159. channel@8 {
  160. gw,mode = <3>;
  161. reg = <0x08>;
  162. label = "vdd_bat";
  163. };
  164. channel@82 {
  165. gw,mode = <2>;
  166. reg = <0x82>;
  167. label = "vdd_vin";
  168. gw,voltage-divider-ohms = <22100 1000>;
  169. gw,voltage-offset-microvolt = <800000>;
  170. };
  171. channel@84 {
  172. gw,mode = <2>;
  173. reg = <0x84>;
  174. label = "vdd_5p0";
  175. gw,voltage-divider-ohms = <22100 10000>;
  176. };
  177. channel@86 {
  178. gw,mode = <2>;
  179. reg = <0x86>;
  180. label = "vdd_3p3";
  181. gw,voltage-divider-ohms = <10000 10000>;
  182. };
  183. channel@88 {
  184. gw,mode = <2>;
  185. reg = <0x88>;
  186. label = "vdd_2p5";
  187. gw,voltage-divider-ohms = <10000 10000>;
  188. };
  189. channel@8c {
  190. gw,mode = <2>;
  191. reg = <0x8c>;
  192. label = "vdd_3p0";
  193. };
  194. channel@8e {
  195. gw,mode = <2>;
  196. reg = <0x8e>;
  197. label = "vdd_arm";
  198. };
  199. channel@90 {
  200. gw,mode = <2>;
  201. reg = <0x90>;
  202. label = "vdd_soc";
  203. };
  204. channel@92 {
  205. gw,mode = <2>;
  206. reg = <0x92>;
  207. label = "vdd_1p5";
  208. };
  209. channel@98 {
  210. gw,mode = <2>;
  211. reg = <0x98>;
  212. label = "vdd_1p8";
  213. };
  214. channel@9a {
  215. gw,mode = <2>;
  216. reg = <0x9a>;
  217. label = "vdd_1p0";
  218. gw,voltage-divider-ohms = <10000 10000>;
  219. };
  220. channel@9c {
  221. gw,mode = <2>;
  222. reg = <0x9c>;
  223. label = "vdd_an1";
  224. gw,voltage-divider-ohms = <10000 10000>;
  225. };
  226. channel@a2 {
  227. gw,mode = <2>;
  228. reg = <0xa2>;
  229. label = "vdd_gsc";
  230. gw,voltage-divider-ohms = <10000 10000>;
  231. };
  232. };
  233. };
  234. gsc_gpio: gpio@23 {
  235. compatible = "nxp,pca9555";
  236. reg = <0x23>;
  237. gpio-controller;
  238. #gpio-cells = <2>;
  239. interrupt-parent = <&gsc>;
  240. interrupts = <4>;
  241. };
  242. eeprom@50 {
  243. compatible = "atmel,24c02";
  244. reg = <0x50>;
  245. pagesize = <16>;
  246. };
  247. eeprom@51 {
  248. compatible = "atmel,24c02";
  249. reg = <0x51>;
  250. pagesize = <16>;
  251. };
  252. eeprom@52 {
  253. compatible = "atmel,24c02";
  254. reg = <0x52>;
  255. pagesize = <16>;
  256. };
  257. eeprom@53 {
  258. compatible = "atmel,24c02";
  259. reg = <0x53>;
  260. pagesize = <16>;
  261. };
  262. rtc@68 {
  263. compatible = "dallas,ds1672";
  264. reg = <0x68>;
  265. };
  266. };
  267. &i2c2 {
  268. clock-frequency = <100000>;
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&pinctrl_i2c2>;
  271. status = "okay";
  272. };
  273. &i2c3 {
  274. clock-frequency = <100000>;
  275. pinctrl-names = "default";
  276. pinctrl-0 = <&pinctrl_i2c3>;
  277. status = "okay";
  278. accel@19 {
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&pinctrl_accel>;
  281. compatible = "st,lis2de12";
  282. reg = <0x19>;
  283. st,drdy-int-pin = <1>;
  284. interrupt-parent = <&gpio7>;
  285. interrupts = <13 0>;
  286. interrupt-names = "INT1";
  287. };
  288. };
  289. &pcie {
  290. pinctrl-names = "default";
  291. pinctrl-0 = <&pinctrl_pcie>;
  292. reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
  293. status = "okay";
  294. };
  295. &pwm2 {
  296. pinctrl-names = "default";
  297. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  298. status = "disabled";
  299. };
  300. &pwm3 {
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  303. status = "disabled";
  304. };
  305. /* off-board RS232 */
  306. &uart1 {
  307. pinctrl-names = "default";
  308. pinctrl-0 = <&pinctrl_uart1>;
  309. status = "okay";
  310. };
  311. /* serial console */
  312. &uart2 {
  313. pinctrl-names = "default";
  314. pinctrl-0 = <&pinctrl_uart2>;
  315. status = "okay";
  316. };
  317. /* cc1352 */
  318. &uart3 {
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_uart3>;
  321. uart-has-rtscts;
  322. status = "okay";
  323. };
  324. /* Sterling-LWB Bluetooth */
  325. &uart4 {
  326. pinctrl-names = "default";
  327. pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
  328. uart-has-rtscts;
  329. status = "okay";
  330. bluetooth {
  331. compatible = "brcm,bcm4330-bt";
  332. shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  333. };
  334. };
  335. /* GPS */
  336. &uart5 {
  337. pinctrl-names = "default";
  338. pinctrl-0 = <&pinctrl_uart5>;
  339. status = "okay";
  340. };
  341. &usbotg {
  342. vbus-supply = <&reg_5p0v>;
  343. pinctrl-names = "default";
  344. pinctrl-0 = <&pinctrl_usbotg>;
  345. disable-over-current;
  346. dr_mode = "host";
  347. status = "okay";
  348. };
  349. &usbh1 {
  350. status = "okay";
  351. };
  352. /* Sterling-LWB SDIO WiFi */
  353. &usdhc2 {
  354. pinctrl-names = "default";
  355. pinctrl-0 = <&pinctrl_usdhc2>;
  356. vmmc-supply = <&reg_wl>;
  357. non-removable;
  358. bus-width = <4>;
  359. status = "okay";
  360. };
  361. &usdhc3 {
  362. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  363. pinctrl-0 = <&pinctrl_usdhc3>;
  364. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  365. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  366. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  367. vmmc-supply = <&reg_3p3v>;
  368. status = "okay";
  369. };
  370. &wdog1 {
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_wdog>;
  373. fsl,ext-reset-output;
  374. };
  375. &iomuxc {
  376. pinctrl_accel: accelmuxgrp {
  377. fsl,pins = <
  378. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
  379. >;
  380. };
  381. pinctrl_bten: btengrp {
  382. fsl,pins = <
  383. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
  384. >;
  385. };
  386. pinctrl_ecspi3: escpi3grp {
  387. fsl,pins = <
  388. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  389. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  390. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  391. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
  392. >;
  393. };
  394. pinctrl_enet: enetgrp {
  395. fsl,pins = <
  396. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  397. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  398. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  399. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  400. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  401. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  402. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  403. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  404. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  405. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  406. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  407. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  408. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  409. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  410. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  411. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  412. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  413. >;
  414. };
  415. pinctrl_gpio_leds: gpioledsgrp {
  416. fsl,pins = <
  417. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  418. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  419. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  420. >;
  421. };
  422. pinctrl_gpmi_nand: gpminandgrp {
  423. fsl,pins = <
  424. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  425. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  426. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  427. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  428. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  429. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  430. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  431. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  432. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  433. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  434. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  435. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  436. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  437. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  438. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  439. >;
  440. };
  441. pinctrl_i2c1: i2c1grp {
  442. fsl,pins = <
  443. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  444. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  445. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
  446. >;
  447. };
  448. pinctrl_i2c2: i2c2grp {
  449. fsl,pins = <
  450. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  451. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  452. >;
  453. };
  454. pinctrl_i2c3: i2c3grp {
  455. fsl,pins = <
  456. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  457. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  458. >;
  459. };
  460. pinctrl_pcie: pciegrp {
  461. fsl,pins = <
  462. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
  463. >;
  464. };
  465. pinctrl_pps: ppsgrp {
  466. fsl,pins = <
  467. MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
  468. >;
  469. };
  470. pinctrl_pwm2: pwm2grp {
  471. fsl,pins = <
  472. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  473. >;
  474. };
  475. pinctrl_pwm3: pwm3grp {
  476. fsl,pins = <
  477. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  478. >;
  479. };
  480. pinctrl_reg_wl: regwlgrp {
  481. fsl,pins = <
  482. MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
  483. >;
  484. };
  485. pinctrl_uart1: uart1grp {
  486. fsl,pins = <
  487. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  488. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  489. >;
  490. };
  491. pinctrl_uart2: uart2grp {
  492. fsl,pins = <
  493. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  494. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  495. >;
  496. };
  497. pinctrl_uart3: uart3grp {
  498. fsl,pins = <
  499. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  500. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  501. MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
  502. MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
  503. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
  504. MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
  505. MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
  506. MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
  507. MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
  508. MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
  509. MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
  510. MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
  511. >;
  512. };
  513. pinctrl_uart4: uart4grp {
  514. fsl,pins = <
  515. MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
  516. MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
  517. MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
  518. MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
  519. >;
  520. };
  521. pinctrl_uart5: uart5grp {
  522. fsl,pins = <
  523. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  524. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  525. >;
  526. };
  527. pinctrl_usbotg: usbotggrp {
  528. fsl,pins = <
  529. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
  530. >;
  531. };
  532. pinctrl_usdhc2: usdhc2grp {
  533. fsl,pins = <
  534. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  535. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  536. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  537. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  538. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  539. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  540. >;
  541. };
  542. pinctrl_usdhc3: usdhc3grp {
  543. fsl,pins = <
  544. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  545. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  546. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  547. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  548. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  549. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  550. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  551. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  552. >;
  553. };
  554. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  555. fsl,pins = <
  556. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  557. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
  558. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  559. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  560. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  561. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  562. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  563. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  564. >;
  565. };
  566. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  567. fsl,pins = <
  568. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  569. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  570. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  571. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  572. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  573. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  574. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  575. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  576. >;
  577. };
  578. pinctrl_wdog: wdoggrp {
  579. fsl,pins = <
  580. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  581. >;
  582. };
  583. };