imx6qdl-gw5904.dtsi 18 KB

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  1. /*
  2. * Copyright 2017 Gateworks Corporation
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public
  20. * License along with this file; if not, write to the Free
  21. * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. *
  24. * Or, alternatively,
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use,
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include <dt-bindings/gpio/gpio.h>
  48. #include <dt-bindings/input/linux-event-codes.h>
  49. #include <dt-bindings/interrupt-controller/irq.h>
  50. / {
  51. /* these are used by bootloader for disabling nodes */
  52. aliases {
  53. led0 = &led0;
  54. led1 = &led1;
  55. led2 = &led2;
  56. mmc0 = &usdhc3;
  57. usb0 = &usbh1;
  58. usb1 = &usbotg;
  59. };
  60. chosen {
  61. stdout-path = &uart2;
  62. };
  63. backlight {
  64. compatible = "pwm-backlight";
  65. pwms = <&pwm4 0 5000000>;
  66. brightness-levels = <0 4 8 16 32 64 128 255>;
  67. default-brightness-level = <7>;
  68. };
  69. gpio-keys {
  70. compatible = "gpio-keys";
  71. #address-cells = <1>;
  72. #size-cells = <0>;
  73. user-pb {
  74. label = "user_pb";
  75. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  76. linux,code = <BTN_0>;
  77. };
  78. user-pb1x {
  79. label = "user_pb1x";
  80. linux,code = <BTN_1>;
  81. interrupt-parent = <&gsc>;
  82. interrupts = <0>;
  83. };
  84. key-erased {
  85. label = "key-erased";
  86. linux,code = <BTN_2>;
  87. interrupt-parent = <&gsc>;
  88. interrupts = <1>;
  89. };
  90. eeprom-wp {
  91. label = "eeprom_wp";
  92. linux,code = <BTN_3>;
  93. interrupt-parent = <&gsc>;
  94. interrupts = <2>;
  95. };
  96. tamper {
  97. label = "tamper";
  98. linux,code = <BTN_4>;
  99. interrupt-parent = <&gsc>;
  100. interrupts = <5>;
  101. };
  102. switch-hold {
  103. label = "switch_hold";
  104. linux,code = <BTN_5>;
  105. interrupt-parent = <&gsc>;
  106. interrupts = <7>;
  107. };
  108. };
  109. leds {
  110. compatible = "gpio-leds";
  111. pinctrl-names = "default";
  112. pinctrl-0 = <&pinctrl_gpio_leds>;
  113. led0: user1 {
  114. label = "user1";
  115. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  116. default-state = "on";
  117. linux,default-trigger = "heartbeat";
  118. };
  119. led1: user2 {
  120. label = "user2";
  121. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  122. default-state = "off";
  123. };
  124. led2: user3 {
  125. label = "user3";
  126. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  127. default-state = "off";
  128. };
  129. };
  130. memory@10000000 {
  131. device_type = "memory";
  132. reg = <0x10000000 0x40000000>;
  133. };
  134. pps {
  135. compatible = "pps-gpio";
  136. pinctrl-names = "default";
  137. pinctrl-0 = <&pinctrl_pps>;
  138. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  139. };
  140. reg_1p0v: regulator-1p0v {
  141. compatible = "regulator-fixed";
  142. regulator-name = "1P0V";
  143. regulator-min-microvolt = <1000000>;
  144. regulator-max-microvolt = <1000000>;
  145. regulator-always-on;
  146. };
  147. reg_3p3v: regulator-3p3v {
  148. compatible = "regulator-fixed";
  149. regulator-name = "3P3V";
  150. regulator-min-microvolt = <3300000>;
  151. regulator-max-microvolt = <3300000>;
  152. regulator-always-on;
  153. };
  154. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  155. compatible = "regulator-fixed";
  156. regulator-name = "usb_h1_vbus";
  157. regulator-min-microvolt = <5000000>;
  158. regulator-max-microvolt = <5000000>;
  159. regulator-always-on;
  160. };
  161. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  162. compatible = "regulator-fixed";
  163. regulator-name = "usb_otg_vbus";
  164. regulator-min-microvolt = <5000000>;
  165. regulator-max-microvolt = <5000000>;
  166. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  167. enable-active-high;
  168. };
  169. };
  170. &clks {
  171. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  172. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  173. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  174. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  175. };
  176. &fec {
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_enet>;
  179. phy-mode = "rgmii-id";
  180. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  181. phy-reset-duration = <10>;
  182. phy-reset-post-delay = <100>;
  183. status = "okay";
  184. fixed-link {
  185. speed = <1000>;
  186. full-duplex;
  187. };
  188. mdio {
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. switch@0 {
  192. compatible = "marvell,mv88e6085";
  193. reg = <0>;
  194. ports {
  195. #address-cells = <1>;
  196. #size-cells = <0>;
  197. port@0 {
  198. reg = <0>;
  199. label = "lan4";
  200. };
  201. port@1 {
  202. reg = <1>;
  203. label = "lan3";
  204. };
  205. port@2 {
  206. reg = <2>;
  207. label = "lan2";
  208. };
  209. port@3 {
  210. reg = <3>;
  211. label = "lan1";
  212. };
  213. port@5 {
  214. reg = <5>;
  215. label = "cpu";
  216. ethernet = <&fec>;
  217. };
  218. };
  219. };
  220. };
  221. };
  222. &i2c1 {
  223. clock-frequency = <100000>;
  224. pinctrl-names = "default";
  225. pinctrl-0 = <&pinctrl_i2c1>;
  226. status = "okay";
  227. gsc: gsc@20 {
  228. compatible = "gw,gsc";
  229. reg = <0x20>;
  230. interrupt-parent = <&gpio1>;
  231. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  232. interrupt-controller;
  233. #interrupt-cells = <1>;
  234. #size-cells = <0>;
  235. adc {
  236. compatible = "gw,gsc-adc";
  237. #address-cells = <1>;
  238. #size-cells = <0>;
  239. channel@0 {
  240. gw,mode = <0>;
  241. reg = <0x00>;
  242. label = "temp";
  243. };
  244. channel@2 {
  245. gw,mode = <1>;
  246. reg = <0x02>;
  247. label = "vdd_vin";
  248. };
  249. channel@5 {
  250. gw,mode = <1>;
  251. reg = <0x05>;
  252. label = "vdd_3p3";
  253. };
  254. channel@8 {
  255. gw,mode = <1>;
  256. reg = <0x08>;
  257. label = "vdd_bat";
  258. };
  259. channel@b {
  260. gw,mode = <1>;
  261. reg = <0x0b>;
  262. label = "vdd_5p0";
  263. };
  264. channel@e {
  265. gw,mode = <1>;
  266. reg = <0xe>;
  267. label = "vdd_arm";
  268. };
  269. channel@11 {
  270. gw,mode = <1>;
  271. reg = <0x11>;
  272. label = "vdd_soc";
  273. };
  274. channel@14 {
  275. gw,mode = <1>;
  276. reg = <0x14>;
  277. label = "vdd_3p0";
  278. };
  279. channel@17 {
  280. gw,mode = <1>;
  281. reg = <0x17>;
  282. label = "vdd_1p5";
  283. };
  284. channel@1d {
  285. gw,mode = <1>;
  286. reg = <0x1d>;
  287. label = "vdd_1p8";
  288. };
  289. channel@20 {
  290. gw,mode = <1>;
  291. reg = <0x20>;
  292. label = "vdd_an1";
  293. };
  294. channel@23 {
  295. gw,mode = <1>;
  296. reg = <0x23>;
  297. label = "vdd_2p5";
  298. };
  299. };
  300. };
  301. gsc_gpio: gpio@23 {
  302. compatible = "nxp,pca9555";
  303. reg = <0x23>;
  304. gpio-controller;
  305. #gpio-cells = <2>;
  306. interrupt-parent = <&gsc>;
  307. interrupts = <4>;
  308. };
  309. eeprom1: eeprom@50 {
  310. compatible = "atmel,24c02";
  311. reg = <0x50>;
  312. pagesize = <16>;
  313. };
  314. eeprom2: eeprom@51 {
  315. compatible = "atmel,24c02";
  316. reg = <0x51>;
  317. pagesize = <16>;
  318. };
  319. eeprom3: eeprom@52 {
  320. compatible = "atmel,24c02";
  321. reg = <0x52>;
  322. pagesize = <16>;
  323. };
  324. eeprom4: eeprom@53 {
  325. compatible = "atmel,24c02";
  326. reg = <0x53>;
  327. pagesize = <16>;
  328. };
  329. dts1672: rtc@68 {
  330. compatible = "dallas,ds1672";
  331. reg = <0x68>;
  332. };
  333. };
  334. &i2c2 {
  335. clock-frequency = <100000>;
  336. pinctrl-names = "default";
  337. pinctrl-0 = <&pinctrl_i2c2>;
  338. status = "okay";
  339. magn@1c {
  340. compatible = "st,lsm9ds1-magn";
  341. reg = <0x1c>;
  342. pinctrl-names = "default";
  343. pinctrl-0 = <&pinctrl_mag>;
  344. interrupt-parent = <&gpio5>;
  345. interrupts = <17 IRQ_TYPE_EDGE_RISING>;
  346. };
  347. ltc3676: pmic@3c {
  348. compatible = "lltc,ltc3676";
  349. reg = <0x3c>;
  350. interrupt-parent = <&gpio1>;
  351. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  352. regulators {
  353. /* VDD_SOC (1+R1/R2 = 1.635) */
  354. reg_vdd_soc: sw1 {
  355. regulator-name = "vddsoc";
  356. regulator-min-microvolt = <674400>;
  357. regulator-max-microvolt = <1308000>;
  358. lltc,fb-voltage-divider = <127000 200000>;
  359. regulator-ramp-delay = <7000>;
  360. regulator-boot-on;
  361. regulator-always-on;
  362. };
  363. /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
  364. reg_1p8v: sw2 {
  365. regulator-name = "vdd1p8";
  366. regulator-min-microvolt = <1033310>;
  367. regulator-max-microvolt = <2004000>;
  368. lltc,fb-voltage-divider = <301000 200000>;
  369. regulator-ramp-delay = <7000>;
  370. regulator-boot-on;
  371. regulator-always-on;
  372. };
  373. /* VDD_ARM (1+R1/R2 = 1.635) */
  374. reg_vdd_arm: sw3 {
  375. regulator-name = "vddarm";
  376. regulator-min-microvolt = <674400>;
  377. regulator-max-microvolt = <1308000>;
  378. lltc,fb-voltage-divider = <127000 200000>;
  379. regulator-ramp-delay = <7000>;
  380. regulator-boot-on;
  381. regulator-always-on;
  382. };
  383. /* VDD_DDR (1+R1/R2 = 2.105) */
  384. reg_vdd_ddr: sw4 {
  385. regulator-name = "vddddr";
  386. regulator-min-microvolt = <868310>;
  387. regulator-max-microvolt = <1684000>;
  388. lltc,fb-voltage-divider = <221000 200000>;
  389. regulator-ramp-delay = <7000>;
  390. regulator-boot-on;
  391. regulator-always-on;
  392. };
  393. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  394. reg_2p5v: ldo2 {
  395. regulator-name = "vdd2p5";
  396. regulator-min-microvolt = <2490375>;
  397. regulator-max-microvolt = <2490375>;
  398. lltc,fb-voltage-divider = <487000 200000>;
  399. regulator-boot-on;
  400. regulator-always-on;
  401. };
  402. /* VDD_HIGH (1+R1/R2 = 4.17) */
  403. reg_3p0v: ldo4 {
  404. regulator-name = "vdd3p0";
  405. regulator-min-microvolt = <3023250>;
  406. regulator-max-microvolt = <3023250>;
  407. lltc,fb-voltage-divider = <634000 200000>;
  408. regulator-boot-on;
  409. regulator-always-on;
  410. };
  411. };
  412. };
  413. imu@6a {
  414. compatible = "st,lsm9ds1-imu";
  415. reg = <0x6a>;
  416. st,drdy-int-pin = <1>;
  417. pinctrl-names = "default";
  418. pinctrl-0 = <&pinctrl_imu>;
  419. interrupt-parent = <&gpio4>;
  420. interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
  421. };
  422. };
  423. &i2c3 {
  424. clock-frequency = <100000>;
  425. pinctrl-names = "default";
  426. pinctrl-0 = <&pinctrl_i2c3>;
  427. status = "okay";
  428. egalax_ts: touchscreen@4 {
  429. compatible = "eeti,egalax_ts";
  430. reg = <0x04>;
  431. interrupt-parent = <&gpio1>;
  432. interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
  433. wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
  434. };
  435. };
  436. &ldb {
  437. status = "okay";
  438. lvds-channel@0 {
  439. fsl,data-mapping = "spwg";
  440. fsl,data-width = <18>;
  441. status = "okay";
  442. display-timings {
  443. native-mode = <&timing0>;
  444. timing0: hsd100pxn1 {
  445. clock-frequency = <65000000>;
  446. hactive = <1024>;
  447. vactive = <768>;
  448. hback-porch = <220>;
  449. hfront-porch = <40>;
  450. vback-porch = <21>;
  451. vfront-porch = <7>;
  452. hsync-len = <60>;
  453. vsync-len = <10>;
  454. };
  455. };
  456. };
  457. };
  458. &pcie {
  459. pinctrl-names = "default";
  460. pinctrl-0 = <&pinctrl_pcie>;
  461. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  462. status = "okay";
  463. };
  464. &pwm2 {
  465. pinctrl-names = "default";
  466. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  467. status = "disabled";
  468. };
  469. &pwm3 {
  470. pinctrl-names = "default";
  471. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  472. status = "disabled";
  473. };
  474. &pwm4 {
  475. #pwm-cells = <2>;
  476. pinctrl-names = "default";
  477. pinctrl-0 = <&pinctrl_pwm4>;
  478. status = "okay";
  479. };
  480. &uart1 {
  481. pinctrl-names = "default";
  482. pinctrl-0 = <&pinctrl_uart1>;
  483. status = "okay";
  484. };
  485. &uart2 {
  486. pinctrl-names = "default";
  487. pinctrl-0 = <&pinctrl_uart2>;
  488. status = "okay";
  489. };
  490. &uart3 {
  491. pinctrl-names = "default";
  492. pinctrl-0 = <&pinctrl_uart3>;
  493. uart-has-rtscts;
  494. status = "okay";
  495. };
  496. &uart4 {
  497. pinctrl-names = "default";
  498. pinctrl-0 = <&pinctrl_uart4>;
  499. uart-has-rtscts;
  500. status = "okay";
  501. };
  502. &uart5 {
  503. pinctrl-names = "default";
  504. pinctrl-0 = <&pinctrl_uart5>;
  505. status = "okay";
  506. };
  507. &usbotg {
  508. vbus-supply = <&reg_usb_otg_vbus>;
  509. pinctrl-names = "default";
  510. pinctrl-0 = <&pinctrl_usbotg>;
  511. disable-over-current;
  512. dr_mode = "otg";
  513. status = "okay";
  514. };
  515. &usbh1 {
  516. vbus-supply = <&reg_usb_h1_vbus>;
  517. status = "okay";
  518. };
  519. &usdhc3 {
  520. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  521. pinctrl-0 = <&pinctrl_usdhc3>;
  522. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  523. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  524. non-removable;
  525. vmmc-supply = <&reg_3p3v>;
  526. keep-power-in-suspend;
  527. status = "okay";
  528. };
  529. &wdog1 {
  530. pinctrl-names = "default";
  531. pinctrl-0 = <&pinctrl_wdog>;
  532. fsl,ext-reset-output;
  533. };
  534. &iomuxc {
  535. pinctrl_enet: enetgrp {
  536. fsl,pins = <
  537. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  538. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  539. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  540. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  541. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  542. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  543. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  544. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  545. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  546. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  547. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  548. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  549. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  550. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  551. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  552. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  553. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
  554. >;
  555. };
  556. pinctrl_gpio_leds: gpioledsgrp {
  557. fsl,pins = <
  558. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  559. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  560. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  561. >;
  562. };
  563. pinctrl_i2c1: i2c1grp {
  564. fsl,pins = <
  565. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  566. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  567. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
  568. >;
  569. };
  570. pinctrl_i2c2: i2c2grp {
  571. fsl,pins = <
  572. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  573. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  574. >;
  575. };
  576. pinctrl_i2c3: i2c3grp {
  577. fsl,pins = <
  578. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  579. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  580. >;
  581. };
  582. pinctrl_imu: imugrp {
  583. fsl,pins = <
  584. MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
  585. >;
  586. };
  587. pinctrl_mag: maggrp {
  588. fsl,pins = <
  589. MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
  590. >;
  591. };
  592. pinctrl_pcie: pciegrp {
  593. fsl,pins = <
  594. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
  595. >;
  596. };
  597. pinctrl_pmic: pmicgrp {
  598. fsl,pins = <
  599. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */
  600. >;
  601. };
  602. pinctrl_pps: ppsgrp {
  603. fsl,pins = <
  604. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  605. >;
  606. };
  607. pinctrl_pwm2: pwm2grp {
  608. fsl,pins = <
  609. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  610. >;
  611. };
  612. pinctrl_pwm3: pwm3grp {
  613. fsl,pins = <
  614. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  615. >;
  616. };
  617. pinctrl_pwm4: pwm4grp {
  618. fsl,pins = <
  619. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  620. >;
  621. };
  622. pinctrl_uart1: uart1grp {
  623. fsl,pins = <
  624. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  625. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  626. >;
  627. };
  628. pinctrl_uart2: uart2grp {
  629. fsl,pins = <
  630. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  631. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  632. >;
  633. };
  634. pinctrl_uart3: uart3grp {
  635. fsl,pins = <
  636. MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
  637. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  638. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  639. MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
  640. >;
  641. };
  642. pinctrl_uart4: uart4grp {
  643. fsl,pins = <
  644. MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
  645. MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
  646. MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
  647. MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
  648. >;
  649. };
  650. pinctrl_uart5: uart5grp {
  651. fsl,pins = <
  652. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  653. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  654. >;
  655. };
  656. pinctrl_usbotg: usbotggrp {
  657. fsl,pins = <
  658. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  659. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
  660. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
  661. >;
  662. };
  663. pinctrl_usdhc3: usdhc3grp {
  664. fsl,pins = <
  665. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  666. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  667. MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
  668. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  669. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  670. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  671. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  672. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  673. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  674. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  675. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  676. >;
  677. };
  678. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  679. fsl,pins = <
  680. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  681. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  682. MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
  683. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  684. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  685. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  686. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  687. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
  688. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
  689. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
  690. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
  691. >;
  692. };
  693. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  694. fsl,pins = <
  695. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  696. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  697. MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
  698. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  699. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  700. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  701. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  702. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
  703. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
  704. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
  705. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
  706. >;
  707. };
  708. pinctrl_wdog: wdoggrp {
  709. fsl,pins = <
  710. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  711. >;
  712. };
  713. };