imx6qdl-gw5903.dtsi 19 KB

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  1. /*
  2. * Copyright 2017 Gateworks Corporation
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public
  20. * License along with this file; if not, write to the Free
  21. * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. *
  24. * Or, alternatively,
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use,
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include <dt-bindings/gpio/gpio.h>
  48. #include <dt-bindings/input/linux-event-codes.h>
  49. #include <dt-bindings/interrupt-controller/irq.h>
  50. / {
  51. chosen {
  52. stdout-path = &uart2;
  53. };
  54. backlight {
  55. compatible = "pwm-backlight";
  56. pwms = <&pwm1 0 5000000>;
  57. brightness-levels = <
  58. 0 1 2 3 4 5 6 7 8 9
  59. 10 11 12 13 14 15 16 17 18 19
  60. 20 21 22 23 24 25 26 27 28 29
  61. 30 31 32 33 34 35 36 37 38 39
  62. 40 41 42 43 44 45 46 47 48 49
  63. 50 51 52 53 54 55 56 57 58 59
  64. 60 61 62 63 64 65 66 67 68 69
  65. 70 71 72 73 74 75 76 77 78 79
  66. 80 81 82 83 84 85 86 87 88 89
  67. 90 91 92 93 94 95 96 97 98 99
  68. 100
  69. >;
  70. default-brightness-level = <100>;
  71. };
  72. gpio-keys {
  73. compatible = "gpio-keys";
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. user-pb {
  77. label = "user_pb";
  78. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  79. linux,code = <BTN_0>;
  80. };
  81. user-pb1x {
  82. label = "user_pb1x";
  83. linux,code = <BTN_1>;
  84. interrupt-parent = <&gsc>;
  85. interrupts = <0>;
  86. };
  87. key-erased {
  88. label = "key-erased";
  89. linux,code = <BTN_2>;
  90. interrupt-parent = <&gsc>;
  91. interrupts = <1>;
  92. };
  93. eeprom-wp {
  94. label = "eeprom_wp";
  95. linux,code = <BTN_3>;
  96. interrupt-parent = <&gsc>;
  97. interrupts = <2>;
  98. };
  99. tamper {
  100. label = "tamper";
  101. linux,code = <BTN_4>;
  102. interrupt-parent = <&gsc>;
  103. interrupts = <5>;
  104. };
  105. switch-hold {
  106. label = "switch_hold";
  107. linux,code = <BTN_5>;
  108. interrupt-parent = <&gsc>;
  109. interrupts = <7>;
  110. };
  111. };
  112. leds {
  113. compatible = "gpio-leds";
  114. pinctrl-names = "default";
  115. pinctrl-0 = <&pinctrl_gpio_leds>;
  116. led0: user1 {
  117. label = "user1";
  118. gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  119. default-state = "off";
  120. };
  121. };
  122. memory@10000000 {
  123. device_type = "memory";
  124. reg = <0x10000000 0x40000000>;
  125. };
  126. reg_5p0v: regulator-5p0v {
  127. compatible = "regulator-fixed";
  128. regulator-name = "5P0V";
  129. regulator-min-microvolt = <5000000>;
  130. regulator-max-microvolt = <5000000>;
  131. regulator-always-on;
  132. };
  133. reg_3p3v: regulator-3p3v {
  134. compatible = "regulator-fixed";
  135. regulator-name = "3P3V";
  136. regulator-min-microvolt = <3300000>;
  137. regulator-max-microvolt = <3300000>;
  138. regulator-always-on;
  139. };
  140. reg_2p5v: regulator-2p5v {
  141. compatible = "regulator-fixed";
  142. regulator-name = "2P5V";
  143. regulator-min-microvolt = <2500000>;
  144. regulator-max-microvolt = <2500000>;
  145. regulator-always-on;
  146. };
  147. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  148. compatible = "regulator-fixed";
  149. regulator-name = "usb_h1_vbus";
  150. regulator-min-microvolt = <5000000>;
  151. regulator-max-microvolt = <5000000>;
  152. gpio = <&gpio3 30 0>;
  153. enable-active-high;
  154. };
  155. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  156. compatible = "regulator-fixed";
  157. regulator-name = "usb_otg_vbus";
  158. regulator-min-microvolt = <5000000>;
  159. regulator-max-microvolt = <5000000>;
  160. gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
  161. enable-active-high;
  162. };
  163. reg_12p0: regulator-12p0v {
  164. compatible = "regulator-fixed";
  165. regulator-name = "12P0V";
  166. regulator-min-microvolt = <12000000>;
  167. regulator-max-microvolt = <12000000>;
  168. gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  169. enable-active-high;
  170. };
  171. sound {
  172. compatible = "fsl,imx-audio-tlv320";
  173. model = "imx-tlv320";
  174. ssi-controller = <&ssi1>;
  175. audio-codec = <&tlv320aic3105>;
  176. /* routing of sink, source */
  177. audio-routing =
  178. /* TLV320 LINE1L pin <-> Mic Jack connector */
  179. "LINE1L", "Mic Jack",
  180. /* board Headphone Jack <-> HPOUT */
  181. "Headphone Jack", "HPLOUT",
  182. "Headphone Jack", "HPROUT",
  183. "Mic Jack", "Mic Bias";
  184. mux-int-port = <1>;
  185. mux-ext-port = <6>;
  186. };
  187. };
  188. &audmux {
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&pinctrl_audmux>;
  191. status = "okay";
  192. };
  193. &clks {
  194. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  195. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  196. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  197. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  198. };
  199. &fec {
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&pinctrl_enet>;
  202. phy-mode = "rgmii-id";
  203. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  204. phy-reset-duration = <10>;
  205. phy-reset-post-delay = <100>;
  206. status = "okay";
  207. };
  208. &i2c1 {
  209. clock-frequency = <100000>;
  210. pinctrl-names = "default";
  211. pinctrl-0 = <&pinctrl_i2c1>;
  212. status = "okay";
  213. gsc: gsc@20 {
  214. compatible = "gw,gsc";
  215. reg = <0x20>;
  216. interrupt-parent = <&gpio1>;
  217. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  218. interrupt-controller;
  219. #interrupt-cells = <1>;
  220. #size-cells = <0>;
  221. adc {
  222. compatible = "gw,gsc-adc";
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. channel@0 {
  226. gw,mode = <0>;
  227. reg = <0x00>;
  228. label = "temp";
  229. };
  230. channel@2 {
  231. gw,mode = <1>;
  232. reg = <0x02>;
  233. label = "vdd_vin";
  234. };
  235. channel@5 {
  236. gw,mode = <1>;
  237. reg = <0x05>;
  238. label = "vdd_3p3";
  239. };
  240. channel@8 {
  241. gw,mode = <1>;
  242. reg = <0x08>;
  243. label = "vdd_bat";
  244. };
  245. channel@b {
  246. gw,mode = <1>;
  247. reg = <0x0b>;
  248. label = "vdd_5p0";
  249. };
  250. channel@e {
  251. gw,mode = <1>;
  252. reg = <0xe>;
  253. label = "vdd_arm";
  254. };
  255. channel@11 {
  256. gw,mode = <1>;
  257. reg = <0x11>;
  258. label = "vdd_soc";
  259. };
  260. channel@14 {
  261. gw,mode = <1>;
  262. reg = <0x14>;
  263. label = "vdd_3p0";
  264. };
  265. channel@17 {
  266. gw,mode = <1>;
  267. reg = <0x17>;
  268. label = "vdd_1p5";
  269. };
  270. channel@1d {
  271. gw,mode = <1>;
  272. reg = <0x1d>;
  273. label = "vdd_1p8";
  274. };
  275. channel@20 {
  276. gw,mode = <1>;
  277. reg = <0x20>;
  278. label = "vdd_an1";
  279. };
  280. channel@23 {
  281. gw,mode = <1>;
  282. reg = <0x23>;
  283. label = "vdd_2p5";
  284. };
  285. };
  286. };
  287. gsc_gpio: gpio@23 {
  288. compatible = "nxp,pca9555";
  289. reg = <0x23>;
  290. gpio-controller;
  291. #gpio-cells = <2>;
  292. interrupt-parent = <&gsc>;
  293. interrupts = <4>;
  294. };
  295. eeprom1: eeprom@50 {
  296. compatible = "atmel,24c02";
  297. reg = <0x50>;
  298. pagesize = <16>;
  299. };
  300. eeprom2: eeprom@51 {
  301. compatible = "atmel,24c02";
  302. reg = <0x51>;
  303. pagesize = <16>;
  304. };
  305. eeprom3: eeprom@52 {
  306. compatible = "atmel,24c02";
  307. reg = <0x52>;
  308. pagesize = <16>;
  309. };
  310. eeprom4: eeprom@53 {
  311. compatible = "atmel,24c02";
  312. reg = <0x53>;
  313. pagesize = <16>;
  314. };
  315. dts1672: rtc@68 {
  316. compatible = "dallas,ds1672";
  317. reg = <0x68>;
  318. };
  319. };
  320. &i2c2 {
  321. clock-frequency = <400000>;
  322. pinctrl-names = "default";
  323. pinctrl-0 = <&pinctrl_i2c2>;
  324. status = "okay";
  325. ltc3676: pmic@3c {
  326. compatible = "lltc,ltc3676";
  327. reg = <0x3c>;
  328. interrupt-parent = <&gpio1>;
  329. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  330. regulators {
  331. /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
  332. reg_1p8v: sw1 {
  333. regulator-name = "vdd1p8";
  334. regulator-min-microvolt = <1033310>;
  335. regulator-max-microvolt = <2004000>;
  336. lltc,fb-voltage-divider = <301000 200000>;
  337. regulator-ramp-delay = <7000>;
  338. regulator-boot-on;
  339. regulator-always-on;
  340. };
  341. /* VDD_DDR (1+R1/R2 = 2.105) */
  342. reg_vdd_ddr: sw2 {
  343. regulator-name = "vddddr";
  344. regulator-min-microvolt = <868310>;
  345. regulator-max-microvolt = <1684000>;
  346. lltc,fb-voltage-divider = <221000 200000>;
  347. regulator-ramp-delay = <7000>;
  348. regulator-boot-on;
  349. regulator-always-on;
  350. };
  351. /* VDD_ARM (1+R1/R2 = 1.635) */
  352. reg_vdd_arm: sw3 {
  353. regulator-name = "vddarm";
  354. regulator-min-microvolt = <674400>;
  355. regulator-max-microvolt = <1308000>;
  356. lltc,fb-voltage-divider = <127000 200000>;
  357. regulator-ramp-delay = <7000>;
  358. regulator-boot-on;
  359. regulator-always-on;
  360. linux,phandle = <&reg_vdd_arm>;
  361. };
  362. /* VDD_SOC (1+R1/R2 = 1.635) */
  363. reg_vdd_soc: sw4 {
  364. regulator-name = "vddsoc";
  365. regulator-min-microvolt = <674400>;
  366. regulator-max-microvolt = <1308000>;
  367. lltc,fb-voltage-divider = <127000 200000>;
  368. regulator-ramp-delay = <7000>;
  369. regulator-boot-on;
  370. regulator-always-on;
  371. linux,phandle = <&reg_vdd_soc>;
  372. };
  373. /* VDD_1P0 (1+R1/R2 = 1.38): */
  374. reg_1p0v: ldo2 {
  375. regulator-name = "vdd1p0";
  376. regulator-min-microvolt = <1002777>;
  377. regulator-max-microvolt = <1002777>;
  378. lltc,fb-voltage-divider = <100000 261000>;
  379. regulator-boot-on;
  380. regulator-always-on;
  381. };
  382. /* VDD_HIGH (1+R1/R2 = 4.17) */
  383. reg_3p0v: ldo4 {
  384. regulator-name = "vdd3p0";
  385. regulator-min-microvolt = <3023250>;
  386. regulator-max-microvolt = <3023250>;
  387. lltc,fb-voltage-divider = <634000 200000>;
  388. regulator-boot-on;
  389. regulator-always-on;
  390. };
  391. };
  392. };
  393. };
  394. &i2c3 {
  395. clock-frequency = <400000>;
  396. pinctrl-names = "default";
  397. pinctrl-0 = <&pinctrl_i2c3>;
  398. status = "okay";
  399. tlv320aic3105: codec@18 {
  400. compatible = "ti,tlv320aic3x";
  401. reg = <0x18>;
  402. reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
  403. clocks = <&clks IMX6QDL_CLK_CKO>;
  404. ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
  405. /* Regulators */
  406. DRVDD-supply = <&reg_3p3v>;
  407. AVDD-supply = <&reg_3p3v>;
  408. IOVDD-supply = <&reg_3p3v>;
  409. DVDD-supply = <&reg_1p8v>;
  410. };
  411. accelerometer@1d {
  412. compatible = "fsl,mma8451";
  413. reg = <0x1d>;
  414. interrupt-parent = <&gpio7>;
  415. interrupts = <11 IRQ_TYPE_EDGE_RISING>;
  416. interrupt-names = "INT2";
  417. };
  418. /* headphone detect */
  419. ts3a227e@3b {
  420. compatible = "ti,ts3a227e";
  421. reg = <0x3b>;
  422. interrupt-parent = <&gpio5>;
  423. interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
  424. ti,micbias = <4>; /* 2.5V micbias */
  425. };
  426. };
  427. &ldb {
  428. status = "okay";
  429. lvds-channel@0 {
  430. fsl,data-mapping = "spwg";
  431. fsl,data-width = <18>;
  432. status = "okay";
  433. display-timings {
  434. native-mode = <&timing0>;
  435. timing0: g101evn010 {
  436. clock-frequency = <68930000>;
  437. hactive = <1280>;
  438. vactive = <800>;
  439. hback-porch = <220>;
  440. hfront-porch = <40>;
  441. vback-porch = <21>;
  442. vfront-porch = <7>;
  443. hsync-len = <60>;
  444. vsync-len = <10>;
  445. };
  446. };
  447. };
  448. };
  449. &pwm1 {
  450. #pwm-cells = <2>;
  451. pinctrl-names = "default";
  452. pinctrl-0 = <&pinctrl_pwm1>;
  453. status = "okay";
  454. };
  455. &ssi1 {
  456. status = "okay";
  457. };
  458. &uart1 {
  459. pinctrl-names = "default";
  460. pinctrl-0 = <&pinctrl_uart1>;
  461. status = "okay";
  462. };
  463. &uart2 {
  464. pinctrl-names = "default";
  465. pinctrl-0 = <&pinctrl_uart2>;
  466. status = "okay";
  467. };
  468. &usbotg {
  469. vbus-supply = <&reg_usb_otg_vbus>;
  470. pinctrl-names = "default";
  471. pinctrl-0 = <&pinctrl_usbotg>;
  472. disable-over-current;
  473. dr_mode = "host";
  474. status = "okay";
  475. };
  476. &usbh1 {
  477. vbus-supply = <&reg_usb_h1_vbus>;
  478. status = "okay";
  479. };
  480. &usdhc1 {
  481. pinctrl-names = "default";
  482. pinctrl-0 = <&pinctrl_usdhc1_200mhz>;
  483. vmmc-supply = <&reg_3p3v>;
  484. non-removable;
  485. bus-width = <4>;
  486. status = "okay";
  487. };
  488. &usdhc2 {
  489. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  490. pinctrl-0 = <&pinctrl_usdhc2>;
  491. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  492. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  493. cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  494. vmmc-supply = <&reg_3p3v>;
  495. max-frequency = <100000000>;
  496. status = "okay";
  497. };
  498. &usdhc3 {
  499. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  500. pinctrl-0 = <&pinctrl_usdhc3>;
  501. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  502. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  503. non-removable;
  504. vmmc-supply = <&reg_3p3v>;
  505. keep-power-in-suspend;
  506. status = "okay";
  507. };
  508. &wdog1 {
  509. pinctrl-names = "default";
  510. pinctrl-0 = <&pinctrl_wdog>;
  511. fsl,ext-reset-output;
  512. };
  513. &iomuxc {
  514. pinctrl_audmux: audmuxgrp {
  515. fsl,pins = <
  516. MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
  517. MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
  518. MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
  519. MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
  520. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */
  521. >;
  522. };
  523. pinctrl_enet: enetgrp {
  524. fsl,pins = <
  525. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  526. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  527. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  528. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  529. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  530. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  531. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  532. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  533. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  534. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  535. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  536. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  537. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  538. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  539. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  540. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
  541. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */
  542. >;
  543. };
  544. pinctrl_gpio_leds: gpioledsgrp {
  545. fsl,pins = <
  546. MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
  547. >;
  548. };
  549. pinctrl_i2c1: i2c1grp {
  550. fsl,pins = <
  551. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  552. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  553. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
  554. >;
  555. };
  556. pinctrl_i2c2: i2c2grp {
  557. fsl,pins = <
  558. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  559. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  560. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  561. >;
  562. };
  563. pinctrl_i2c3: i2c3grp {
  564. fsl,pins = <
  565. /* I2C3 */
  566. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  567. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  568. /* Headphone Detect */
  569. MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */
  570. MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */
  571. /* Codec */
  572. MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */
  573. /* Touch Controller */
  574. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */
  575. MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */
  576. /* Stow Sensor */
  577. MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */
  578. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */
  579. >;
  580. };
  581. pinctrl_pwm1: pwm1grp {
  582. fsl,pins = <
  583. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  584. >;
  585. };
  586. pinctrl_uart1: uart1grp {
  587. fsl,pins = <
  588. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  589. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  590. MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */
  591. >;
  592. };
  593. pinctrl_uart2: uart2grp {
  594. fsl,pins = <
  595. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  596. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  597. >;
  598. };
  599. pinctrl_usbotg: usbotggrp {
  600. fsl,pins = <
  601. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
  602. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */
  603. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
  604. >;
  605. };
  606. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  607. fsl,pins = <
  608. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */
  609. MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */
  610. MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */
  611. MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */
  612. MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */
  613. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
  614. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9
  615. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
  616. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
  617. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
  618. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
  619. >;
  620. };
  621. pinctrl_usdhc2: usdhc2grp {
  622. fsl,pins = <
  623. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  624. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  625. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  626. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  627. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  628. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  629. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */
  630. MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059
  631. >;
  632. };
  633. pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  634. fsl,pins = <
  635. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
  636. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
  637. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
  638. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
  639. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
  640. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
  641. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */
  642. MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9
  643. >;
  644. };
  645. pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  646. fsl,pins = <
  647. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
  648. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
  649. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
  650. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
  651. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
  652. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
  653. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */
  654. MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9
  655. >;
  656. };
  657. pinctrl_usdhc3: usdhc3grp {
  658. fsl,pins = <
  659. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  660. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  661. MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
  662. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  663. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  664. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  665. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  666. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  667. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  668. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  669. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  670. >;
  671. };
  672. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  673. fsl,pins = <
  674. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  675. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  676. MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
  677. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  678. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  679. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  680. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  681. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
  682. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
  683. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
  684. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
  685. >;
  686. };
  687. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  688. fsl,pins = <
  689. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  690. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  691. MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
  692. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  693. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  694. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  695. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  696. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
  697. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
  698. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
  699. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
  700. >;
  701. };
  702. pinctrl_wdog: wdoggrp {
  703. fsl,pins = <
  704. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  705. >;
  706. };
  707. };