imx6qdl-gw54xx.dtsi 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/sound/fsl-imx-audmux.h>
  9. / {
  10. /* these are used by bootloader for disabling nodes */
  11. aliases {
  12. led0 = &led0;
  13. led1 = &led1;
  14. led2 = &led2;
  15. mmc0 = &usdhc3;
  16. nand = &gpmi;
  17. ssi0 = &ssi1;
  18. usb0 = &usbh1;
  19. usb1 = &usbotg;
  20. };
  21. chosen {
  22. bootargs = "console=ttymxc1,115200";
  23. };
  24. backlight {
  25. compatible = "pwm-backlight";
  26. pwms = <&pwm4 0 5000000>;
  27. brightness-levels = <0 4 8 16 32 64 128 255>;
  28. default-brightness-level = <7>;
  29. };
  30. gpio-keys {
  31. compatible = "gpio-keys";
  32. #address-cells = <1>;
  33. #size-cells = <0>;
  34. user-pb {
  35. label = "user_pb";
  36. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  37. linux,code = <BTN_0>;
  38. };
  39. user-pb1x {
  40. label = "user_pb1x";
  41. linux,code = <BTN_1>;
  42. interrupt-parent = <&gsc>;
  43. interrupts = <0>;
  44. };
  45. key-erased {
  46. label = "key-erased";
  47. linux,code = <BTN_2>;
  48. interrupt-parent = <&gsc>;
  49. interrupts = <1>;
  50. };
  51. eeprom-wp {
  52. label = "eeprom_wp";
  53. linux,code = <BTN_3>;
  54. interrupt-parent = <&gsc>;
  55. interrupts = <2>;
  56. };
  57. tamper {
  58. label = "tamper";
  59. linux,code = <BTN_4>;
  60. interrupt-parent = <&gsc>;
  61. interrupts = <5>;
  62. };
  63. switch-hold {
  64. label = "switch_hold";
  65. linux,code = <BTN_5>;
  66. interrupt-parent = <&gsc>;
  67. interrupts = <7>;
  68. };
  69. };
  70. leds {
  71. compatible = "gpio-leds";
  72. pinctrl-names = "default";
  73. pinctrl-0 = <&pinctrl_gpio_leds>;
  74. led0: user1 {
  75. label = "user1";
  76. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  77. default-state = "on";
  78. linux,default-trigger = "heartbeat";
  79. };
  80. led1: user2 {
  81. label = "user2";
  82. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  83. default-state = "off";
  84. };
  85. led2: user3 {
  86. label = "user3";
  87. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  88. default-state = "off";
  89. };
  90. };
  91. memory@10000000 {
  92. device_type = "memory";
  93. reg = <0x10000000 0x40000000>;
  94. };
  95. pps {
  96. compatible = "pps-gpio";
  97. pinctrl-names = "default";
  98. pinctrl-0 = <&pinctrl_pps>;
  99. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  100. status = "okay";
  101. };
  102. regulators {
  103. compatible = "simple-bus";
  104. #address-cells = <1>;
  105. #size-cells = <0>;
  106. reg_1p0v: regulator@0 {
  107. compatible = "regulator-fixed";
  108. reg = <0>;
  109. regulator-name = "1P0V";
  110. regulator-min-microvolt = <1000000>;
  111. regulator-max-microvolt = <1000000>;
  112. regulator-always-on;
  113. };
  114. reg_3p3v: regulator@1 {
  115. compatible = "regulator-fixed";
  116. reg = <1>;
  117. regulator-name = "3P3V";
  118. regulator-min-microvolt = <3300000>;
  119. regulator-max-microvolt = <3300000>;
  120. regulator-always-on;
  121. };
  122. reg_usb_h1_vbus: regulator@2 {
  123. compatible = "regulator-fixed";
  124. reg = <2>;
  125. regulator-name = "usb_h1_vbus";
  126. regulator-min-microvolt = <5000000>;
  127. regulator-max-microvolt = <5000000>;
  128. regulator-always-on;
  129. };
  130. reg_usb_otg_vbus: regulator@3 {
  131. compatible = "regulator-fixed";
  132. reg = <3>;
  133. regulator-name = "usb_otg_vbus";
  134. regulator-min-microvolt = <5000000>;
  135. regulator-max-microvolt = <5000000>;
  136. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  137. enable-active-high;
  138. };
  139. };
  140. sound-analog {
  141. compatible = "fsl,imx6q-ventana-sgtl5000",
  142. "fsl,imx-audio-sgtl5000";
  143. model = "sgtl5000-audio";
  144. ssi-controller = <&ssi1>;
  145. audio-codec = <&sgtl5000>;
  146. audio-routing =
  147. "MIC_IN", "Mic Jack",
  148. "Mic Jack", "Mic Bias",
  149. "Headphone Jack", "HP_OUT";
  150. mux-int-port = <1>;
  151. mux-ext-port = <4>;
  152. };
  153. };
  154. &audmux {
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
  157. status = "okay";
  158. ssi2 {
  159. fsl,audmux-port = <1>;
  160. fsl,port-config = <
  161. (IMX_AUDMUX_V2_PTCR_TFSDIR |
  162. IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
  163. IMX_AUDMUX_V2_PTCR_TCLKDIR |
  164. IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
  165. IMX_AUDMUX_V2_PTCR_SYN)
  166. IMX_AUDMUX_V2_PDCR_RXDSEL(4)
  167. >;
  168. };
  169. aud5 {
  170. fsl,audmux-port = <4>;
  171. fsl,port-config = <
  172. IMX_AUDMUX_V2_PTCR_SYN
  173. IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
  174. };
  175. };
  176. &can1 {
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_flexcan1>;
  179. status = "okay";
  180. };
  181. &clks {
  182. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  183. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  184. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  185. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  186. };
  187. &ecspi2 {
  188. cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&pinctrl_ecspi2>;
  191. status = "okay";
  192. };
  193. &fec {
  194. pinctrl-names = "default";
  195. pinctrl-0 = <&pinctrl_enet>;
  196. phy-mode = "rgmii-id";
  197. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  198. phy-reset-duration = <10>;
  199. phy-reset-post-delay = <100>;
  200. status = "okay";
  201. };
  202. &gpmi {
  203. pinctrl-names = "default";
  204. pinctrl-0 = <&pinctrl_gpmi_nand>;
  205. status = "okay";
  206. };
  207. &hdmi {
  208. ddc-i2c-bus = <&i2c3>;
  209. status = "okay";
  210. };
  211. &i2c1 {
  212. clock-frequency = <100000>;
  213. pinctrl-names = "default";
  214. pinctrl-0 = <&pinctrl_i2c1>;
  215. status = "okay";
  216. gsc: gsc@20 {
  217. compatible = "gw,gsc";
  218. reg = <0x20>;
  219. interrupt-parent = <&gpio1>;
  220. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  221. interrupt-controller;
  222. #interrupt-cells = <1>;
  223. #address-cells = <1>;
  224. #size-cells = <0>;
  225. adc {
  226. compatible = "gw,gsc-adc";
  227. #address-cells = <1>;
  228. #size-cells = <0>;
  229. channel@0 {
  230. gw,mode = <0>;
  231. reg = <0x00>;
  232. label = "temp";
  233. };
  234. channel@2 {
  235. gw,mode = <1>;
  236. reg = <0x02>;
  237. label = "vdd_vin";
  238. };
  239. channel@5 {
  240. gw,mode = <1>;
  241. reg = <0x05>;
  242. label = "vdd_3p3";
  243. };
  244. channel@8 {
  245. gw,mode = <1>;
  246. reg = <0x08>;
  247. label = "vdd_bat";
  248. };
  249. channel@b {
  250. gw,mode = <1>;
  251. reg = <0x0b>;
  252. label = "vdd_5p0";
  253. };
  254. channel@e {
  255. gw,mode = <1>;
  256. reg = <0xe>;
  257. label = "vdd_arm";
  258. };
  259. channel@11 {
  260. gw,mode = <1>;
  261. reg = <0x11>;
  262. label = "vdd_soc";
  263. };
  264. channel@14 {
  265. gw,mode = <1>;
  266. reg = <0x14>;
  267. label = "vdd_3p0";
  268. };
  269. channel@17 {
  270. gw,mode = <1>;
  271. reg = <0x17>;
  272. label = "vdd_1p5";
  273. };
  274. channel@1d {
  275. gw,mode = <1>;
  276. reg = <0x1d>;
  277. label = "vdd_1p8";
  278. };
  279. channel@20 {
  280. gw,mode = <1>;
  281. reg = <0x20>;
  282. label = "vdd_1p0";
  283. };
  284. channel@23 {
  285. gw,mode = <1>;
  286. reg = <0x23>;
  287. label = "vdd_2p5";
  288. };
  289. channel@26 {
  290. gw,mode = <1>;
  291. reg = <0x26>;
  292. label = "vdd_gps";
  293. };
  294. };
  295. fan-controller@2c {
  296. compatible = "gw,gsc-fan";
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. reg = <0x2c>;
  300. };
  301. };
  302. gsc_gpio: gpio@23 {
  303. compatible = "nxp,pca9555";
  304. reg = <0x23>;
  305. gpio-controller;
  306. #gpio-cells = <2>;
  307. interrupt-parent = <&gsc>;
  308. interrupts = <4>;
  309. };
  310. eeprom1: eeprom@50 {
  311. compatible = "atmel,24c02";
  312. reg = <0x50>;
  313. pagesize = <16>;
  314. };
  315. eeprom2: eeprom@51 {
  316. compatible = "atmel,24c02";
  317. reg = <0x51>;
  318. pagesize = <16>;
  319. };
  320. eeprom3: eeprom@52 {
  321. compatible = "atmel,24c02";
  322. reg = <0x52>;
  323. pagesize = <16>;
  324. };
  325. eeprom4: eeprom@53 {
  326. compatible = "atmel,24c02";
  327. reg = <0x53>;
  328. pagesize = <16>;
  329. };
  330. rtc: ds1672@68 {
  331. compatible = "dallas,ds1672";
  332. reg = <0x68>;
  333. };
  334. };
  335. &i2c2 {
  336. clock-frequency = <100000>;
  337. pinctrl-names = "default";
  338. pinctrl-0 = <&pinctrl_i2c2>;
  339. status = "okay";
  340. pmic: pfuze100@8 {
  341. compatible = "fsl,pfuze100";
  342. reg = <0x08>;
  343. regulators {
  344. sw1a_reg: sw1ab {
  345. regulator-min-microvolt = <300000>;
  346. regulator-max-microvolt = <1875000>;
  347. regulator-boot-on;
  348. regulator-always-on;
  349. regulator-ramp-delay = <6250>;
  350. };
  351. sw1c_reg: sw1c {
  352. regulator-min-microvolt = <300000>;
  353. regulator-max-microvolt = <1875000>;
  354. regulator-boot-on;
  355. regulator-always-on;
  356. regulator-ramp-delay = <6250>;
  357. };
  358. sw2_reg: sw2 {
  359. regulator-min-microvolt = <800000>;
  360. regulator-max-microvolt = <3950000>;
  361. regulator-boot-on;
  362. regulator-always-on;
  363. };
  364. sw3a_reg: sw3a {
  365. regulator-min-microvolt = <400000>;
  366. regulator-max-microvolt = <1975000>;
  367. regulator-boot-on;
  368. regulator-always-on;
  369. };
  370. sw3b_reg: sw3b {
  371. regulator-min-microvolt = <400000>;
  372. regulator-max-microvolt = <1975000>;
  373. regulator-boot-on;
  374. regulator-always-on;
  375. };
  376. sw4_reg: sw4 {
  377. regulator-min-microvolt = <800000>;
  378. regulator-max-microvolt = <3300000>;
  379. };
  380. swbst_reg: swbst {
  381. regulator-min-microvolt = <5000000>;
  382. regulator-max-microvolt = <5150000>;
  383. regulator-boot-on;
  384. regulator-always-on;
  385. };
  386. snvs_reg: vsnvs {
  387. regulator-min-microvolt = <1000000>;
  388. regulator-max-microvolt = <3000000>;
  389. regulator-boot-on;
  390. regulator-always-on;
  391. };
  392. vref_reg: vrefddr {
  393. regulator-boot-on;
  394. regulator-always-on;
  395. };
  396. vgen1_reg: vgen1 {
  397. regulator-min-microvolt = <800000>;
  398. regulator-max-microvolt = <1550000>;
  399. };
  400. vgen2_reg: vgen2 {
  401. regulator-min-microvolt = <800000>;
  402. regulator-max-microvolt = <1550000>;
  403. };
  404. vgen3_reg: vgen3 {
  405. regulator-min-microvolt = <1800000>;
  406. regulator-max-microvolt = <3300000>;
  407. };
  408. vgen4_reg: vgen4 {
  409. regulator-min-microvolt = <1800000>;
  410. regulator-max-microvolt = <3300000>;
  411. regulator-always-on;
  412. };
  413. vgen5_reg: vgen5 {
  414. regulator-min-microvolt = <1800000>;
  415. regulator-max-microvolt = <3300000>;
  416. regulator-always-on;
  417. };
  418. vgen6_reg: vgen6 {
  419. regulator-min-microvolt = <1800000>;
  420. regulator-max-microvolt = <3300000>;
  421. regulator-always-on;
  422. };
  423. };
  424. };
  425. };
  426. &i2c3 {
  427. clock-frequency = <100000>;
  428. pinctrl-names = "default";
  429. pinctrl-0 = <&pinctrl_i2c3>;
  430. status = "okay";
  431. sgtl5000: audio-codec@a {
  432. compatible = "fsl,sgtl5000";
  433. reg = <0x0a>;
  434. clocks = <&clks IMX6QDL_CLK_CKO>;
  435. VDDA-supply = <&sw4_reg>;
  436. VDDIO-supply = <&reg_3p3v>;
  437. };
  438. touchscreen: egalax_ts@4 {
  439. compatible = "eeti,egalax_ts";
  440. reg = <0x04>;
  441. interrupt-parent = <&gpio7>;
  442. interrupts = <12 2>;
  443. wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
  444. };
  445. accel@1e {
  446. compatible = "nxp,fxos8700";
  447. reg = <0x1e>;
  448. };
  449. };
  450. &ldb {
  451. status = "okay";
  452. lvds-channel@0 {
  453. fsl,data-mapping = "spwg";
  454. fsl,data-width = <18>;
  455. status = "okay";
  456. display-timings {
  457. native-mode = <&timing0>;
  458. timing0: hsd100pxn1 {
  459. clock-frequency = <65000000>;
  460. hactive = <1024>;
  461. vactive = <768>;
  462. hback-porch = <220>;
  463. hfront-porch = <40>;
  464. vback-porch = <21>;
  465. vfront-porch = <7>;
  466. hsync-len = <60>;
  467. vsync-len = <10>;
  468. };
  469. };
  470. };
  471. };
  472. &pcie {
  473. pinctrl-names = "default";
  474. pinctrl-0 = <&pinctrl_pcie>;
  475. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  476. status = "okay";
  477. };
  478. &pwm1 {
  479. pinctrl-names = "default";
  480. pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
  481. status = "disabled";
  482. };
  483. &pwm2 {
  484. pinctrl-names = "default";
  485. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  486. status = "disabled";
  487. };
  488. &pwm3 {
  489. pinctrl-names = "default";
  490. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  491. status = "disabled";
  492. };
  493. &pwm4 {
  494. #pwm-cells = <2>;
  495. pinctrl-names = "default", "state_dio";
  496. pinctrl-0 = <&pinctrl_pwm4_backlight>;
  497. pinctrl-1 = <&pinctrl_pwm4_dio>;
  498. status = "okay";
  499. };
  500. &ssi1 {
  501. status = "okay";
  502. };
  503. &ssi2 {
  504. status = "okay";
  505. };
  506. &uart1 {
  507. pinctrl-names = "default";
  508. pinctrl-0 = <&pinctrl_uart1>;
  509. rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  510. status = "okay";
  511. };
  512. &uart2 {
  513. pinctrl-names = "default";
  514. pinctrl-0 = <&pinctrl_uart2>;
  515. status = "okay";
  516. };
  517. &uart5 {
  518. pinctrl-names = "default";
  519. pinctrl-0 = <&pinctrl_uart5>;
  520. status = "okay";
  521. };
  522. &usbotg {
  523. vbus-supply = <&reg_usb_otg_vbus>;
  524. pinctrl-names = "default";
  525. pinctrl-0 = <&pinctrl_usbotg>;
  526. disable-over-current;
  527. dr_mode = "otg";
  528. status = "okay";
  529. };
  530. &usbh1 {
  531. vbus-supply = <&reg_usb_h1_vbus>;
  532. status = "okay";
  533. };
  534. &usdhc3 {
  535. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  536. pinctrl-0 = <&pinctrl_usdhc3>;
  537. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  538. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  539. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  540. vmmc-supply = <&reg_3p3v>;
  541. no-1-8-v; /* firmware will remove if board revision supports */
  542. status = "okay";
  543. };
  544. &wdog1 {
  545. status = "disabled";
  546. };
  547. &wdog2 {
  548. pinctrl-names = "default";
  549. pinctrl-0 = <&pinctrl_wdog>;
  550. fsl,ext-reset-output;
  551. status = "okay";
  552. };
  553. &iomuxc {
  554. pinctrl_audmux: audmuxgrp {
  555. fsl,pins = <
  556. MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
  557. MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
  558. MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
  559. MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
  560. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
  561. MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
  562. MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
  563. MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
  564. >;
  565. };
  566. pinctrl_enet: enetgrp {
  567. fsl,pins = <
  568. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  569. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  570. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  571. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  572. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  573. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  574. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  575. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  576. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  577. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  578. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  579. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  580. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  581. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  582. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  583. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  584. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  585. >;
  586. };
  587. pinctrl_ecspi2: escpi2grp {
  588. fsl,pins = <
  589. MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
  590. MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
  591. MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
  592. MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
  593. >;
  594. };
  595. pinctrl_flexcan1: flexcan1grp {
  596. fsl,pins = <
  597. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  598. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  599. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
  600. >;
  601. };
  602. pinctrl_gpio_leds: gpioledsgrp {
  603. fsl,pins = <
  604. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  605. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  606. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  607. >;
  608. };
  609. pinctrl_gpmi_nand: gpminandgrp {
  610. fsl,pins = <
  611. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  612. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  613. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  614. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  615. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  616. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  617. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  618. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  619. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  620. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  621. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  622. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  623. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  624. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  625. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  626. >;
  627. };
  628. pinctrl_i2c1: i2c1grp {
  629. fsl,pins = <
  630. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  631. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  632. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  633. >;
  634. };
  635. pinctrl_i2c2: i2c2grp {
  636. fsl,pins = <
  637. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  638. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  639. >;
  640. };
  641. pinctrl_i2c3: i2c3grp {
  642. fsl,pins = <
  643. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  644. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  645. >;
  646. };
  647. pinctrl_pcie: pciegrp {
  648. fsl,pins = <
  649. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
  650. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
  651. >;
  652. };
  653. pinctrl_pps: ppsgrp {
  654. fsl,pins = <
  655. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  656. >;
  657. };
  658. pinctrl_pwm1: pwm1grp {
  659. fsl,pins = <
  660. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  661. >;
  662. };
  663. pinctrl_pwm2: pwm2grp {
  664. fsl,pins = <
  665. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  666. >;
  667. };
  668. pinctrl_pwm3: pwm3grp {
  669. fsl,pins = <
  670. MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  671. >;
  672. };
  673. pinctrl_pwm4_backlight: pwm4grpbacklight {
  674. fsl,pins = <
  675. /* LVDS_PWM J6.5 */
  676. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  677. >;
  678. };
  679. pinctrl_pwm4_dio: pwm4grpdio {
  680. fsl,pins = <
  681. /* DIO3 J16.4 */
  682. MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
  683. >;
  684. };
  685. pinctrl_uart1: uart1grp {
  686. fsl,pins = <
  687. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  688. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  689. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
  690. >;
  691. };
  692. pinctrl_uart2: uart2grp {
  693. fsl,pins = <
  694. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  695. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  696. >;
  697. };
  698. pinctrl_uart5: uart5grp {
  699. fsl,pins = <
  700. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  701. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  702. >;
  703. };
  704. pinctrl_usbotg: usbotggrp {
  705. fsl,pins = <
  706. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  707. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
  708. >;
  709. };
  710. pinctrl_usdhc3: usdhc3grp {
  711. fsl,pins = <
  712. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  713. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  714. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  715. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  716. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  717. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  718. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  719. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  720. >;
  721. };
  722. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  723. fsl,pins = <
  724. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  725. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  726. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  727. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  728. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  729. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  730. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  731. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  732. >;
  733. };
  734. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  735. fsl,pins = <
  736. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  737. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  738. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  739. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  740. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  741. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  742. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  743. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  744. >;
  745. };
  746. pinctrl_wdog: wdoggrp {
  747. fsl,pins = <
  748. MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
  749. >;
  750. };
  751. };