imx6qdl-gw53xx.dtsi 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. mmc0 = &usdhc3;
  15. nand = &gpmi;
  16. ssi0 = &ssi1;
  17. usb0 = &usbh1;
  18. usb1 = &usbotg;
  19. };
  20. chosen {
  21. bootargs = "console=ttymxc1,115200";
  22. };
  23. backlight {
  24. compatible = "pwm-backlight";
  25. pwms = <&pwm4 0 5000000>;
  26. brightness-levels = <0 4 8 16 32 64 128 255>;
  27. default-brightness-level = <7>;
  28. };
  29. gpio-keys {
  30. compatible = "gpio-keys";
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. user-pb {
  34. label = "user_pb";
  35. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  36. linux,code = <BTN_0>;
  37. };
  38. user-pb1x {
  39. label = "user_pb1x";
  40. linux,code = <BTN_1>;
  41. interrupt-parent = <&gsc>;
  42. interrupts = <0>;
  43. };
  44. key-erased {
  45. label = "key-erased";
  46. linux,code = <BTN_2>;
  47. interrupt-parent = <&gsc>;
  48. interrupts = <1>;
  49. };
  50. eeprom-wp {
  51. label = "eeprom_wp";
  52. linux,code = <BTN_3>;
  53. interrupt-parent = <&gsc>;
  54. interrupts = <2>;
  55. };
  56. tamper {
  57. label = "tamper";
  58. linux,code = <BTN_4>;
  59. interrupt-parent = <&gsc>;
  60. interrupts = <5>;
  61. };
  62. switch-hold {
  63. label = "switch_hold";
  64. linux,code = <BTN_5>;
  65. interrupt-parent = <&gsc>;
  66. interrupts = <7>;
  67. };
  68. };
  69. leds {
  70. compatible = "gpio-leds";
  71. pinctrl-names = "default";
  72. pinctrl-0 = <&pinctrl_gpio_leds>;
  73. led0: user1 {
  74. label = "user1";
  75. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  76. default-state = "on";
  77. linux,default-trigger = "heartbeat";
  78. };
  79. led1: user2 {
  80. label = "user2";
  81. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  82. default-state = "off";
  83. };
  84. led2: user3 {
  85. label = "user3";
  86. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  87. default-state = "off";
  88. };
  89. };
  90. memory@10000000 {
  91. device_type = "memory";
  92. reg = <0x10000000 0x40000000>;
  93. };
  94. pps {
  95. compatible = "pps-gpio";
  96. pinctrl-names = "default";
  97. pinctrl-0 = <&pinctrl_pps>;
  98. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  99. status = "okay";
  100. };
  101. reg_1p0v: regulator-1p0v {
  102. compatible = "regulator-fixed";
  103. regulator-name = "1P0V";
  104. regulator-min-microvolt = <1000000>;
  105. regulator-max-microvolt = <1000000>;
  106. regulator-always-on;
  107. };
  108. reg_3p3v: regulator-3p3v {
  109. compatible = "regulator-fixed";
  110. regulator-name = "3P3V";
  111. regulator-min-microvolt = <3300000>;
  112. regulator-max-microvolt = <3300000>;
  113. regulator-always-on;
  114. };
  115. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  116. compatible = "regulator-fixed";
  117. regulator-name = "usb_h1_vbus";
  118. regulator-min-microvolt = <5000000>;
  119. regulator-max-microvolt = <5000000>;
  120. regulator-always-on;
  121. };
  122. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  123. compatible = "regulator-fixed";
  124. regulator-name = "usb_otg_vbus";
  125. regulator-min-microvolt = <5000000>;
  126. regulator-max-microvolt = <5000000>;
  127. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  128. enable-active-high;
  129. };
  130. sound {
  131. compatible = "fsl,imx6q-ventana-sgtl5000",
  132. "fsl,imx-audio-sgtl5000";
  133. model = "sgtl5000-audio";
  134. ssi-controller = <&ssi1>;
  135. audio-codec = <&codec>;
  136. audio-routing =
  137. "MIC_IN", "Mic Jack",
  138. "Mic Jack", "Mic Bias",
  139. "Headphone Jack", "HP_OUT";
  140. mux-int-port = <1>;
  141. mux-ext-port = <4>;
  142. };
  143. };
  144. &audmux {
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&pinctrl_audmux>;
  147. status = "okay";
  148. };
  149. &can1 {
  150. pinctrl-names = "default";
  151. pinctrl-0 = <&pinctrl_flexcan1>;
  152. status = "okay";
  153. };
  154. &clks {
  155. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  156. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  157. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  158. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  159. };
  160. &fec {
  161. pinctrl-names = "default";
  162. pinctrl-0 = <&pinctrl_enet>;
  163. phy-mode = "rgmii-id";
  164. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  165. phy-reset-duration = <10>;
  166. phy-reset-post-delay = <100>;
  167. status = "okay";
  168. };
  169. &gpmi {
  170. pinctrl-names = "default";
  171. pinctrl-0 = <&pinctrl_gpmi_nand>;
  172. status = "okay";
  173. };
  174. &hdmi {
  175. ddc-i2c-bus = <&i2c3>;
  176. status = "okay";
  177. };
  178. &i2c1 {
  179. clock-frequency = <100000>;
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&pinctrl_i2c1>;
  182. status = "okay";
  183. gsc: gsc@20 {
  184. compatible = "gw,gsc";
  185. reg = <0x20>;
  186. interrupt-parent = <&gpio1>;
  187. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  188. interrupt-controller;
  189. #interrupt-cells = <1>;
  190. #size-cells = <0>;
  191. adc {
  192. compatible = "gw,gsc-adc";
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. channel@0 {
  196. gw,mode = <0>;
  197. reg = <0x00>;
  198. label = "temp";
  199. };
  200. channel@2 {
  201. gw,mode = <1>;
  202. reg = <0x02>;
  203. label = "vdd_vin";
  204. };
  205. channel@5 {
  206. gw,mode = <1>;
  207. reg = <0x05>;
  208. label = "vdd_3p3";
  209. };
  210. channel@8 {
  211. gw,mode = <1>;
  212. reg = <0x08>;
  213. label = "vdd_bat";
  214. };
  215. channel@b {
  216. gw,mode = <1>;
  217. reg = <0x0b>;
  218. label = "vdd_5p0";
  219. };
  220. channel@e {
  221. gw,mode = <1>;
  222. reg = <0xe>;
  223. label = "vdd_arm";
  224. };
  225. channel@11 {
  226. gw,mode = <1>;
  227. reg = <0x11>;
  228. label = "vdd_soc";
  229. };
  230. channel@14 {
  231. gw,mode = <1>;
  232. reg = <0x14>;
  233. label = "vdd_3p0";
  234. };
  235. channel@17 {
  236. gw,mode = <1>;
  237. reg = <0x17>;
  238. label = "vdd_1p5";
  239. };
  240. channel@1d {
  241. gw,mode = <1>;
  242. reg = <0x1d>;
  243. label = "vdd_1p8";
  244. };
  245. channel@20 {
  246. gw,mode = <1>;
  247. reg = <0x20>;
  248. label = "vdd_1p0";
  249. };
  250. channel@23 {
  251. gw,mode = <1>;
  252. reg = <0x23>;
  253. label = "vdd_2p5";
  254. };
  255. channel@26 {
  256. gw,mode = <1>;
  257. reg = <0x26>;
  258. label = "vdd_gps";
  259. };
  260. channel@29 {
  261. gw,mode = <1>;
  262. reg = <0x29>;
  263. label = "vdd_an1";
  264. };
  265. };
  266. };
  267. gsc_gpio: gpio@23 {
  268. compatible = "nxp,pca9555";
  269. reg = <0x23>;
  270. gpio-controller;
  271. #gpio-cells = <2>;
  272. interrupt-parent = <&gsc>;
  273. interrupts = <4>;
  274. };
  275. eeprom1: eeprom@50 {
  276. compatible = "atmel,24c02";
  277. reg = <0x50>;
  278. pagesize = <16>;
  279. };
  280. eeprom2: eeprom@51 {
  281. compatible = "atmel,24c02";
  282. reg = <0x51>;
  283. pagesize = <16>;
  284. };
  285. eeprom3: eeprom@52 {
  286. compatible = "atmel,24c02";
  287. reg = <0x52>;
  288. pagesize = <16>;
  289. };
  290. eeprom4: eeprom@53 {
  291. compatible = "atmel,24c02";
  292. reg = <0x53>;
  293. pagesize = <16>;
  294. };
  295. rtc: ds1672@68 {
  296. compatible = "dallas,ds1672";
  297. reg = <0x68>;
  298. };
  299. };
  300. &i2c2 {
  301. clock-frequency = <100000>;
  302. pinctrl-names = "default";
  303. pinctrl-0 = <&pinctrl_i2c2>;
  304. status = "okay";
  305. ltc3676: pmic@3c {
  306. compatible = "lltc,ltc3676";
  307. reg = <0x3c>;
  308. interrupt-parent = <&gpio1>;
  309. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  310. regulators {
  311. /* VDD_SOC (1+R1/R2 = 1.635) */
  312. reg_vdd_soc: sw1 {
  313. regulator-name = "vddsoc";
  314. regulator-min-microvolt = <674400>;
  315. regulator-max-microvolt = <1308000>;
  316. lltc,fb-voltage-divider = <127000 200000>;
  317. regulator-ramp-delay = <7000>;
  318. regulator-boot-on;
  319. regulator-always-on;
  320. };
  321. /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
  322. reg_1p8v: sw2 {
  323. regulator-name = "vdd1p8";
  324. regulator-min-microvolt = <1033310>;
  325. regulator-max-microvolt = <2004000>;
  326. lltc,fb-voltage-divider = <301000 200000>;
  327. regulator-ramp-delay = <7000>;
  328. regulator-boot-on;
  329. regulator-always-on;
  330. };
  331. /* VDD_ARM (1+R1/R2 = 1.635) */
  332. reg_vdd_arm: sw3 {
  333. regulator-name = "vddarm";
  334. regulator-min-microvolt = <674400>;
  335. regulator-max-microvolt = <1308000>;
  336. lltc,fb-voltage-divider = <127000 200000>;
  337. regulator-ramp-delay = <7000>;
  338. regulator-boot-on;
  339. regulator-always-on;
  340. };
  341. /* VDD_DDR (1+R1/R2 = 2.105) */
  342. reg_vdd_ddr: sw4 {
  343. regulator-name = "vddddr";
  344. regulator-min-microvolt = <868310>;
  345. regulator-max-microvolt = <1684000>;
  346. lltc,fb-voltage-divider = <221000 200000>;
  347. regulator-ramp-delay = <7000>;
  348. regulator-boot-on;
  349. regulator-always-on;
  350. };
  351. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  352. reg_2p5v: ldo2 {
  353. regulator-name = "vdd2p5";
  354. regulator-min-microvolt = <2490375>;
  355. regulator-max-microvolt = <2490375>;
  356. lltc,fb-voltage-divider = <487000 200000>;
  357. regulator-boot-on;
  358. regulator-always-on;
  359. };
  360. /* VDD_AUD_1P8: Audio codec */
  361. reg_aud_1p8v: ldo3 {
  362. regulator-name = "vdd1p8a";
  363. regulator-min-microvolt = <1800000>;
  364. regulator-max-microvolt = <1800000>;
  365. regulator-boot-on;
  366. };
  367. /* VDD_HIGH (1+R1/R2 = 4.17) */
  368. reg_3p0v: ldo4 {
  369. regulator-name = "vdd3p0";
  370. regulator-min-microvolt = <3023250>;
  371. regulator-max-microvolt = <3023250>;
  372. lltc,fb-voltage-divider = <634000 200000>;
  373. regulator-boot-on;
  374. regulator-always-on;
  375. };
  376. };
  377. };
  378. };
  379. &i2c3 {
  380. clock-frequency = <100000>;
  381. pinctrl-names = "default";
  382. pinctrl-0 = <&pinctrl_i2c3>;
  383. status = "okay";
  384. codec: sgtl5000@a {
  385. compatible = "fsl,sgtl5000";
  386. reg = <0x0a>;
  387. clocks = <&clks IMX6QDL_CLK_CKO>;
  388. VDDA-supply = <&reg_1p8v>;
  389. VDDIO-supply = <&reg_3p3v>;
  390. };
  391. touchscreen: egalax_ts@4 {
  392. compatible = "eeti,egalax_ts";
  393. reg = <0x04>;
  394. interrupt-parent = <&gpio1>;
  395. interrupts = <11 2>;
  396. wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
  397. };
  398. accel@1e {
  399. compatible = "nxp,fxos8700";
  400. reg = <0x1e>;
  401. };
  402. };
  403. &ldb {
  404. status = "okay";
  405. lvds-channel@0 {
  406. fsl,data-mapping = "spwg";
  407. fsl,data-width = <18>;
  408. status = "okay";
  409. display-timings {
  410. native-mode = <&timing0>;
  411. timing0: hsd100pxn1 {
  412. clock-frequency = <65000000>;
  413. hactive = <1024>;
  414. vactive = <768>;
  415. hback-porch = <220>;
  416. hfront-porch = <40>;
  417. vback-porch = <21>;
  418. vfront-porch = <7>;
  419. hsync-len = <60>;
  420. vsync-len = <10>;
  421. };
  422. };
  423. };
  424. };
  425. &pcie {
  426. pinctrl-names = "default";
  427. pinctrl-0 = <&pinctrl_pcie>;
  428. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  429. status = "okay";
  430. };
  431. &pwm2 {
  432. pinctrl-names = "default";
  433. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  434. status = "disabled";
  435. };
  436. &pwm3 {
  437. pinctrl-names = "default";
  438. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  439. status = "disabled";
  440. };
  441. &pwm4 {
  442. #pwm-cells = <2>;
  443. pinctrl-names = "default";
  444. pinctrl-0 = <&pinctrl_pwm4>;
  445. status = "okay";
  446. };
  447. &ssi1 {
  448. status = "okay";
  449. };
  450. &uart1 {
  451. pinctrl-names = "default";
  452. pinctrl-0 = <&pinctrl_uart1>;
  453. rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  454. status = "okay";
  455. };
  456. &uart2 {
  457. pinctrl-names = "default";
  458. pinctrl-0 = <&pinctrl_uart2>;
  459. status = "okay";
  460. };
  461. &uart5 {
  462. pinctrl-names = "default";
  463. pinctrl-0 = <&pinctrl_uart5>;
  464. status = "okay";
  465. };
  466. &usbotg {
  467. vbus-supply = <&reg_usb_otg_vbus>;
  468. pinctrl-names = "default";
  469. pinctrl-0 = <&pinctrl_usbotg>;
  470. disable-over-current;
  471. dr_mode = "otg";
  472. status = "okay";
  473. };
  474. &usbh1 {
  475. vbus-supply = <&reg_usb_h1_vbus>;
  476. status = "okay";
  477. };
  478. &usdhc3 {
  479. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  480. pinctrl-0 = <&pinctrl_usdhc3>;
  481. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  482. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  483. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  484. vmmc-supply = <&reg_3p3v>;
  485. no-1-8-v; /* firmware will remove if board revision supports */
  486. status = "okay";
  487. };
  488. &wdog1 {
  489. pinctrl-names = "default";
  490. pinctrl-0 = <&pinctrl_wdog>;
  491. fsl,ext-reset-output;
  492. };
  493. &iomuxc {
  494. pinctrl_audmux: audmuxgrp {
  495. fsl,pins = <
  496. MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
  497. MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
  498. MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
  499. MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
  500. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
  501. >;
  502. };
  503. pinctrl_enet: enetgrp {
  504. fsl,pins = <
  505. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  506. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  507. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  508. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  509. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  510. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  511. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  512. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  513. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  514. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  515. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  516. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  517. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  518. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  519. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  520. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  521. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  522. >;
  523. };
  524. pinctrl_flexcan1: flexcan1grp {
  525. fsl,pins = <
  526. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  527. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  528. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
  529. >;
  530. };
  531. pinctrl_gpio_leds: gpioledsgrp {
  532. fsl,pins = <
  533. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  534. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  535. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  536. >;
  537. };
  538. pinctrl_gpmi_nand: gpminandgrp {
  539. fsl,pins = <
  540. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  541. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  542. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  543. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  544. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  545. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  546. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  547. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  548. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  549. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  550. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  551. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  552. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  553. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  554. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  555. >;
  556. };
  557. pinctrl_i2c1: i2c1grp {
  558. fsl,pins = <
  559. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  560. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  561. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  562. >;
  563. };
  564. pinctrl_i2c2: i2c2grp {
  565. fsl,pins = <
  566. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  567. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  568. >;
  569. };
  570. pinctrl_i2c3: i2c3grp {
  571. fsl,pins = <
  572. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  573. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  574. >;
  575. };
  576. pinctrl_pcie: pciegrp {
  577. fsl,pins = <
  578. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
  579. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
  580. >;
  581. };
  582. pinctrl_pmic: pmicgrp {
  583. fsl,pins = <
  584. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  585. >;
  586. };
  587. pinctrl_pps: ppsgrp {
  588. fsl,pins = <
  589. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  590. >;
  591. };
  592. pinctrl_pwm2: pwm2grp {
  593. fsl,pins = <
  594. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  595. >;
  596. };
  597. pinctrl_pwm3: pwm3grp {
  598. fsl,pins = <
  599. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  600. >;
  601. };
  602. pinctrl_pwm4: pwm4grp {
  603. fsl,pins = <
  604. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  605. >;
  606. };
  607. pinctrl_uart1: uart1grp {
  608. fsl,pins = <
  609. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  610. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  611. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
  612. >;
  613. };
  614. pinctrl_uart2: uart2grp {
  615. fsl,pins = <
  616. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  617. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  618. >;
  619. };
  620. pinctrl_uart5: uart5grp {
  621. fsl,pins = <
  622. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  623. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  624. >;
  625. };
  626. pinctrl_usbotg: usbotggrp {
  627. fsl,pins = <
  628. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  629. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
  630. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
  631. >;
  632. };
  633. pinctrl_usdhc3: usdhc3grp {
  634. fsl,pins = <
  635. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  636. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  637. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  638. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  639. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  640. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  641. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  642. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  643. >;
  644. };
  645. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  646. fsl,pins = <
  647. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  648. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  649. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  650. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  651. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  652. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  653. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  654. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  655. >;
  656. };
  657. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  658. fsl,pins = <
  659. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  660. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  661. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  662. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  663. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  664. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  665. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  666. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  667. >;
  668. };
  669. pinctrl_wdog: wdoggrp {
  670. fsl,pins = <
  671. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  672. >;
  673. };
  674. };