imx6qdl-gw51xx.dtsi 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. nand = &gpmi;
  14. usb0 = &usbh1;
  15. usb1 = &usbotg;
  16. };
  17. chosen {
  18. bootargs = "console=ttymxc1,115200";
  19. };
  20. gpio-keys {
  21. compatible = "gpio-keys";
  22. user-pb {
  23. label = "user_pb";
  24. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  25. linux,code = <BTN_0>;
  26. };
  27. user-pb1x {
  28. label = "user_pb1x";
  29. linux,code = <BTN_1>;
  30. interrupt-parent = <&gsc>;
  31. interrupts = <0>;
  32. };
  33. key-erased {
  34. label = "key-erased";
  35. linux,code = <BTN_2>;
  36. interrupt-parent = <&gsc>;
  37. interrupts = <1>;
  38. };
  39. eeprom-wp {
  40. label = "eeprom_wp";
  41. linux,code = <BTN_3>;
  42. interrupt-parent = <&gsc>;
  43. interrupts = <2>;
  44. };
  45. tamper {
  46. label = "tamper";
  47. linux,code = <BTN_4>;
  48. interrupt-parent = <&gsc>;
  49. interrupts = <5>;
  50. };
  51. switch-hold {
  52. label = "switch_hold";
  53. linux,code = <BTN_5>;
  54. interrupt-parent = <&gsc>;
  55. interrupts = <7>;
  56. };
  57. };
  58. leds {
  59. compatible = "gpio-leds";
  60. pinctrl-names = "default";
  61. pinctrl-0 = <&pinctrl_gpio_leds>;
  62. led0: user1 {
  63. label = "user1";
  64. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  65. default-state = "on";
  66. linux,default-trigger = "heartbeat";
  67. };
  68. led1: user2 {
  69. label = "user2";
  70. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  71. default-state = "off";
  72. };
  73. };
  74. memory@10000000 {
  75. device_type = "memory";
  76. reg = <0x10000000 0x20000000>;
  77. };
  78. pps {
  79. compatible = "pps-gpio";
  80. pinctrl-names = "default";
  81. pinctrl-0 = <&pinctrl_pps>;
  82. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  83. status = "okay";
  84. };
  85. reg_3p3v: regulator-3p3v {
  86. compatible = "regulator-fixed";
  87. regulator-name = "3P3V";
  88. regulator-min-microvolt = <3300000>;
  89. regulator-max-microvolt = <3300000>;
  90. regulator-always-on;
  91. };
  92. reg_5p0v: regulator-5p0v {
  93. compatible = "regulator-fixed";
  94. regulator-name = "5P0V";
  95. regulator-min-microvolt = <5000000>;
  96. regulator-max-microvolt = <5000000>;
  97. regulator-always-on;
  98. };
  99. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  100. compatible = "regulator-fixed";
  101. regulator-name = "usb_otg_vbus";
  102. regulator-min-microvolt = <5000000>;
  103. regulator-max-microvolt = <5000000>;
  104. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  105. enable-active-high;
  106. };
  107. };
  108. &fec {
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_enet>;
  111. phy-mode = "rgmii-id";
  112. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  113. phy-reset-duration = <10>;
  114. phy-reset-post-delay = <100>;
  115. status = "okay";
  116. };
  117. &gpmi {
  118. pinctrl-names = "default";
  119. pinctrl-0 = <&pinctrl_gpmi_nand>;
  120. status = "okay";
  121. };
  122. &hdmi {
  123. ddc-i2c-bus = <&i2c3>;
  124. status = "okay";
  125. };
  126. &i2c1 {
  127. clock-frequency = <100000>;
  128. pinctrl-names = "default";
  129. pinctrl-0 = <&pinctrl_i2c1>;
  130. status = "okay";
  131. gsc: gsc@20 {
  132. compatible = "gw,gsc";
  133. reg = <0x20>;
  134. interrupt-parent = <&gpio1>;
  135. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  136. interrupt-controller;
  137. #interrupt-cells = <1>;
  138. #size-cells = <0>;
  139. adc {
  140. compatible = "gw,gsc-adc";
  141. #address-cells = <1>;
  142. #size-cells = <0>;
  143. channel@0 {
  144. gw,mode = <0>;
  145. reg = <0x00>;
  146. label = "temp";
  147. };
  148. channel@2 {
  149. gw,mode = <1>;
  150. reg = <0x02>;
  151. label = "vdd_vin";
  152. };
  153. channel@5 {
  154. gw,mode = <1>;
  155. reg = <0x05>;
  156. label = "vdd_3p3";
  157. };
  158. channel@8 {
  159. gw,mode = <1>;
  160. reg = <0x08>;
  161. label = "vdd_bat";
  162. };
  163. channel@b {
  164. gw,mode = <1>;
  165. reg = <0x0b>;
  166. label = "vdd_5p0";
  167. };
  168. channel@e {
  169. gw,mode = <1>;
  170. reg = <0xe>;
  171. label = "vdd_arm";
  172. };
  173. channel@11 {
  174. gw,mode = <1>;
  175. reg = <0x11>;
  176. label = "vdd_soc";
  177. };
  178. channel@14 {
  179. gw,mode = <1>;
  180. reg = <0x14>;
  181. label = "vdd_3p0";
  182. };
  183. channel@17 {
  184. gw,mode = <1>;
  185. reg = <0x17>;
  186. label = "vdd_1p5";
  187. };
  188. channel@1d {
  189. gw,mode = <1>;
  190. reg = <0x1d>;
  191. label = "vdd_1p8";
  192. };
  193. channel@20 {
  194. gw,mode = <1>;
  195. reg = <0x20>;
  196. label = "vdd_an1";
  197. };
  198. channel@23 {
  199. gw,mode = <1>;
  200. reg = <0x23>;
  201. label = "vdd_2p5";
  202. };
  203. };
  204. };
  205. gsc_gpio: gpio@23 {
  206. compatible = "nxp,pca9555";
  207. reg = <0x23>;
  208. gpio-controller;
  209. #gpio-cells = <2>;
  210. interrupt-parent = <&gsc>;
  211. interrupts = <4>;
  212. };
  213. eeprom1: eeprom@50 {
  214. compatible = "atmel,24c02";
  215. reg = <0x50>;
  216. pagesize = <16>;
  217. };
  218. eeprom2: eeprom@51 {
  219. compatible = "atmel,24c02";
  220. reg = <0x51>;
  221. pagesize = <16>;
  222. };
  223. eeprom3: eeprom@52 {
  224. compatible = "atmel,24c02";
  225. reg = <0x52>;
  226. pagesize = <16>;
  227. };
  228. eeprom4: eeprom@53 {
  229. compatible = "atmel,24c02";
  230. reg = <0x53>;
  231. pagesize = <16>;
  232. };
  233. rtc: ds1672@68 {
  234. compatible = "dallas,ds1672";
  235. reg = <0x68>;
  236. };
  237. };
  238. &i2c2 {
  239. clock-frequency = <100000>;
  240. pinctrl-names = "default";
  241. pinctrl-0 = <&pinctrl_i2c2>;
  242. status = "okay";
  243. ltc3676: pmic@3c {
  244. compatible = "lltc,ltc3676";
  245. reg = <0x3c>;
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&pinctrl_pmic>;
  248. interrupt-parent = <&gpio1>;
  249. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  250. regulators {
  251. /* VDD_SOC (1+R1/R2 = 1.635) */
  252. reg_vdd_soc: sw1 {
  253. regulator-name = "vddsoc";
  254. regulator-min-microvolt = <674400>;
  255. regulator-max-microvolt = <1308000>;
  256. lltc,fb-voltage-divider = <127000 200000>;
  257. regulator-ramp-delay = <7000>;
  258. regulator-boot-on;
  259. regulator-always-on;
  260. };
  261. /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
  262. reg_1p8v: sw2 {
  263. regulator-name = "vdd1p8";
  264. regulator-min-microvolt = <1033310>;
  265. regulator-max-microvolt = <2004000>;
  266. lltc,fb-voltage-divider = <301000 200000>;
  267. regulator-ramp-delay = <7000>;
  268. regulator-boot-on;
  269. regulator-always-on;
  270. };
  271. /* VDD_ARM (1+R1/R2 = 1.635) */
  272. reg_vdd_arm: sw3 {
  273. regulator-name = "vddarm";
  274. regulator-min-microvolt = <674400>;
  275. regulator-max-microvolt = <1308000>;
  276. lltc,fb-voltage-divider = <127000 200000>;
  277. regulator-ramp-delay = <7000>;
  278. regulator-boot-on;
  279. regulator-always-on;
  280. };
  281. /* VDD_DDR (1+R1/R2 = 2.105) */
  282. reg_vdd_ddr: sw4 {
  283. regulator-name = "vddddr";
  284. regulator-min-microvolt = <868310>;
  285. regulator-max-microvolt = <1684000>;
  286. lltc,fb-voltage-divider = <221000 200000>;
  287. regulator-ramp-delay = <7000>;
  288. regulator-boot-on;
  289. regulator-always-on;
  290. };
  291. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  292. reg_2p5v: ldo2 {
  293. regulator-name = "vdd2p5";
  294. regulator-min-microvolt = <2490375>;
  295. regulator-max-microvolt = <2490375>;
  296. lltc,fb-voltage-divider = <487000 200000>;
  297. regulator-boot-on;
  298. regulator-always-on;
  299. };
  300. /* VDD_HIGH (1+R1/R2 = 4.17) */
  301. reg_3p0v: ldo4 {
  302. regulator-name = "vdd3p0";
  303. regulator-min-microvolt = <3023250>;
  304. regulator-max-microvolt = <3023250>;
  305. lltc,fb-voltage-divider = <634000 200000>;
  306. regulator-boot-on;
  307. regulator-always-on;
  308. };
  309. };
  310. };
  311. };
  312. &i2c3 {
  313. clock-frequency = <100000>;
  314. pinctrl-names = "default";
  315. pinctrl-0 = <&pinctrl_i2c3>;
  316. status = "okay";
  317. adv7180: camera@20 {
  318. compatible = "adi,adv7180";
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_adv7180>;
  321. reg = <0x20>;
  322. powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
  323. interrupt-parent = <&gpio5>;
  324. interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
  325. port {
  326. adv7180_to_ipu1_csi0_mux: endpoint {
  327. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  328. bus-width = <8>;
  329. };
  330. };
  331. };
  332. };
  333. &ipu1_csi0_from_ipu1_csi0_mux {
  334. bus-width = <8>;
  335. };
  336. &ipu1_csi0_mux_from_parallel_sensor {
  337. remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
  338. bus-width = <8>;
  339. };
  340. &ipu1_csi0 {
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  343. };
  344. &pcie {
  345. pinctrl-names = "default";
  346. pinctrl-0 = <&pinctrl_pcie>;
  347. reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
  348. status = "okay";
  349. };
  350. &pwm2 {
  351. pinctrl-names = "default";
  352. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  353. status = "disabled";
  354. };
  355. &pwm3 {
  356. pinctrl-names = "default";
  357. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  358. status = "disabled";
  359. };
  360. &pwm4 {
  361. pinctrl-names = "default";
  362. pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  363. status = "disabled";
  364. };
  365. &uart1 {
  366. pinctrl-names = "default";
  367. pinctrl-0 = <&pinctrl_uart1>;
  368. status = "okay";
  369. };
  370. &uart2 {
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_uart2>;
  373. status = "okay";
  374. };
  375. &uart3 {
  376. pinctrl-names = "default";
  377. pinctrl-0 = <&pinctrl_uart3>;
  378. status = "okay";
  379. };
  380. &uart5 {
  381. pinctrl-names = "default";
  382. pinctrl-0 = <&pinctrl_uart5>;
  383. status = "okay";
  384. };
  385. &usbotg {
  386. vbus-supply = <&reg_usb_otg_vbus>;
  387. pinctrl-names = "default";
  388. pinctrl-0 = <&pinctrl_usbotg>;
  389. disable-over-current;
  390. dr_mode = "otg";
  391. status = "okay";
  392. };
  393. &usbh1 {
  394. status = "okay";
  395. };
  396. &wdog1 {
  397. pinctrl-names = "default";
  398. pinctrl-0 = <&pinctrl_wdog>;
  399. fsl,ext-reset-output;
  400. };
  401. &iomuxc {
  402. pinctrl_adv7180: adv7180grp {
  403. fsl,pins = <
  404. MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
  405. MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
  406. >;
  407. };
  408. pinctrl_enet: enetgrp {
  409. fsl,pins = <
  410. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  411. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  412. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  413. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  414. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  415. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  416. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  417. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  418. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  419. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  420. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  421. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  422. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  423. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  424. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  425. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  426. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
  427. >;
  428. };
  429. pinctrl_gpio_leds: gpioledsgrp {
  430. fsl,pins = <
  431. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  432. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  433. >;
  434. };
  435. pinctrl_gpmi_nand: gpminandgrp {
  436. fsl,pins = <
  437. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  438. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  439. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  440. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  441. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  442. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  443. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  444. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  445. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  446. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  447. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  448. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  449. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  450. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  451. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  452. >;
  453. };
  454. pinctrl_i2c1: i2c1grp {
  455. fsl,pins = <
  456. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  457. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  458. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
  459. >;
  460. };
  461. pinctrl_i2c2: i2c2grp {
  462. fsl,pins = <
  463. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  464. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  465. >;
  466. };
  467. pinctrl_i2c3: i2c3grp {
  468. fsl,pins = <
  469. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  470. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  471. >;
  472. };
  473. pinctrl_ipu1_csi0: ipu1csi0grp {
  474. fsl,pins = <
  475. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  476. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  477. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  478. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  479. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  480. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  481. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  482. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  483. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
  484. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
  485. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  486. >;
  487. };
  488. pinctrl_pcie: pciegrp {
  489. fsl,pins = <
  490. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
  491. >;
  492. };
  493. pinctrl_pmic: pmicgrp {
  494. fsl,pins = <
  495. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  496. >;
  497. };
  498. pinctrl_pps: ppsgrp {
  499. fsl,pins = <
  500. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  501. >;
  502. };
  503. pinctrl_pwm2: pwm2grp {
  504. fsl,pins = <
  505. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  506. >;
  507. };
  508. pinctrl_pwm3: pwm3grp {
  509. fsl,pins = <
  510. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  511. >;
  512. };
  513. pinctrl_pwm4: pwm4grp {
  514. fsl,pins = <
  515. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  516. >;
  517. };
  518. pinctrl_uart1: uart1grp {
  519. fsl,pins = <
  520. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  521. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  522. >;
  523. };
  524. pinctrl_uart2: uart2grp {
  525. fsl,pins = <
  526. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  527. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  528. >;
  529. };
  530. pinctrl_uart3: uart3grp {
  531. fsl,pins = <
  532. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  533. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  534. >;
  535. };
  536. pinctrl_uart5: uart5grp {
  537. fsl,pins = <
  538. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  539. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  540. >;
  541. };
  542. pinctrl_usbotg: usbotggrp {
  543. fsl,pins = <
  544. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  545. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
  546. >;
  547. };
  548. pinctrl_wdog: wdoggrp {
  549. fsl,pins = <
  550. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  551. >;
  552. };
  553. };