csb272.h 9.3 KB

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  1. /*
  2. * (C) Copyright 2004
  3. * Tolunay Orkun, Nextio Inc., torkun@nextio.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405GP 1 /* This is a PPC405GP CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
  35. #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init() */
  36. #define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
  37. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  38. /*
  39. * OS Bootstrap configuration
  40. *
  41. */
  42. #if 0
  43. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  44. #else
  45. #define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
  46. #endif
  47. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
  48. #if 1
  49. #undef CONFIG_BOOTARGS
  50. #define CONFIG_BOOTCOMMAND \
  51. "setenv bootargs console=ttyS0,38400 debug " \
  52. "root=/dev/ram rw ramdisk_size=4096 " \
  53. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
  54. "bootm fe000000 fe100000"
  55. #endif
  56. #if 0
  57. #undef CONFIG_BOOTARGS
  58. #define CONFIG_BOOTCOMMAND \
  59. "bootp; " \
  60. "setenv bootargs console=ttyS0,38400 debug " \
  61. "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
  62. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
  63. "bootm"
  64. #endif
  65. /*
  66. * BOOTP/DHCP protocol configuration
  67. *
  68. */
  69. #define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
  70. CONFIG_BOOTP_DNS2 | \
  71. CONFIG_BOOTP_BOOTFILESIZE )
  72. /*
  73. * U-Boot Monitor Command Line Functions Configuration
  74. *
  75. */
  76. #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  77. CFG_CMD_ASKENV | \
  78. CFG_CMD_BEDBUG | \
  79. CFG_CMD_ELF | \
  80. CFG_CMD_IRQ | \
  81. CFG_CMD_I2C | \
  82. CFG_CMD_PCI | \
  83. CFG_CMD_DATE | \
  84. CFG_CMD_MII | \
  85. CFG_CMD_PING | \
  86. CFG_CMD_DHCP )
  87. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  88. #include <cmd_confdefs.h>
  89. /*
  90. * Serial download configuration
  91. *
  92. */
  93. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  94. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  95. /*
  96. * KGDB Configuration
  97. *
  98. */
  99. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  100. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  101. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  102. #endif
  103. /*
  104. * Miscellaneous configurable options
  105. *
  106. */
  107. #undef CFG_HUSH_PARSER /* use "hush" command parser */
  108. #ifdef CFG_HUSH_PARSER
  109. #define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
  110. #endif
  111. #define CFG_LONGHELP /* undef to save memory */
  112. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  113. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  114. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  115. #else
  116. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  117. #endif
  118. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  119. #define CFG_MAXARGS 16 /* max number of command args */
  120. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  121. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  122. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  123. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  124. #define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
  125. #define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
  126. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  127. /*
  128. * For booting Linux, the board info and command line data
  129. * have to be in the first 8 MB of memory, since this is
  130. * the maximum mapped by the Linux kernel during initialization.
  131. */
  132. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  133. /*
  134. * watchdog configuration
  135. *
  136. */
  137. #undef CONFIG_WATCHDOG /* watchdog disabled */
  138. /*
  139. * UART configuration
  140. *
  141. */
  142. #define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
  143. #undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
  144. #undef CFG_BASE_BAUD
  145. #define CONFIG_BAUDRATE 38400 /* Default baud rate */
  146. #define CFG_BAUDRATE_TABLE \
  147. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
  148. /*
  149. * I2C configuration
  150. *
  151. */
  152. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  153. #define CFG_I2C_SPEED 100000 /* I2C speed */
  154. #define CFG_I2C_SLAVE 0x7F /* I2C slave address */
  155. /*
  156. * MII PHY configuration
  157. *
  158. */
  159. #define CONFIG_MII 1 /* MII PHY management */
  160. #define CONFIG_PHY_ADDR 0 /* PHY address */
  161. #define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
  162. /* 32usec min. for LXT971A */
  163. #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
  164. /*
  165. * RTC configuration
  166. *
  167. * Note that DS1307 RTC is limited to 100Khz I2C bus.
  168. *
  169. */
  170. #define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
  171. /*
  172. * PCI stuff
  173. *
  174. */
  175. #define CONFIG_PCI /* include pci support */
  176. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  177. #define PCI_HOST_FORCE 1 /* configure as pci host */
  178. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  179. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  180. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  181. /* resource configuration */
  182. #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  183. #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
  184. #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
  185. #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
  186. #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
  187. #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  188. #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  189. #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
  190. #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
  191. #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  192. /*
  193. * IDE stuff
  194. *
  195. */
  196. #undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
  197. #undef CONFIG_IDE_LED /* no led for ide supported */
  198. #undef CONFIG_IDE_RESET /* no reset for ide supported */
  199. /*
  200. * Environment configuration
  201. *
  202. */
  203. #define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
  204. #undef CFG_ENV_IS_IN_NVRAM
  205. #undef CFG_ENV_IS_IN_EEPROM
  206. /*
  207. * General Memory organization
  208. *
  209. * Start addresses for the final memory configuration
  210. * (Set up by the startup code)
  211. * Please note that CFG_SDRAM_BASE _must_ start at 0
  212. */
  213. #define CFG_SDRAM_BASE 0x00000000
  214. #define CFG_FLASH_BASE 0xFE000000
  215. #define CFG_FLASH_SIZE 0x02000000
  216. #define CFG_MONITOR_BASE TEXT_BASE
  217. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
  218. #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
  219. #if CFG_MONITOR_BASE < CFG_FLASH_BASE
  220. #define CFG_RAMSTART
  221. #endif
  222. #if defined(CFG_ENV_IS_IN_FLASH)
  223. #define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
  224. #define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
  225. #define CFG_ENV_SIZE 0x00001000 /* Size of Environment */
  226. #define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
  227. #endif
  228. /*
  229. * FLASH Device configuration
  230. *
  231. */
  232. #define CFG_FLASH_CFI 1 /* flash is CFI conformant */
  233. #define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
  234. #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  235. #define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
  236. #define CFG_FLASH_INCREMENT 0 /* there is only one bank */
  237. #define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
  238. #define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
  239. #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
  240. /*
  241. * On Chip Memory location/size
  242. *
  243. */
  244. #define CFG_OCM_DATA_ADDR 0xF8000000
  245. #define CFG_OCM_DATA_SIZE 0x1000
  246. /*
  247. * Global info and initial stack
  248. *
  249. */
  250. #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
  251. #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
  252. #define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
  253. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  254. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  255. /*
  256. * Cache configuration
  257. *
  258. */
  259. #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  260. /* have only 8kB, 16kB is save here */
  261. #define CFG_CACHELINE_SIZE 32
  262. /*
  263. * Miscellaneous board specific definitions
  264. *
  265. */
  266. #define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
  267. /*
  268. * Internal Definitions
  269. *
  270. * Boot Flags
  271. *
  272. */
  273. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  274. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  275. #endif /* __CONFIG_H */