netarm_mem_module.h 5.2 KB

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  1. /*
  2. * include/asm-armnommu/arch-netarm/netarm_mem_module.h
  3. *
  4. * Copyright (C) 2000, 2001 NETsilicon, Inc.
  5. * Copyright (C) 2000, 2001 Red Hat, Inc.
  6. *
  7. * This software is copyrighted by Red Hat. LICENSEE agrees that
  8. * it will not delete this copyright notice, trademarks or protective
  9. * notices from any copy made by LICENSEE.
  10. *
  11. * This software is provided "AS-IS" and any express or implied
  12. * warranties or conditions, including but not limited to any
  13. * implied warranties of merchantability and fitness for a particular
  14. * purpose regarding this software. In no event shall Red Hat
  15. * be liable for any indirect, consequential, or incidental damages,
  16. * loss of profits or revenue, loss of use or data, or interruption
  17. * of business, whether the alleged damages are labeled in contract,
  18. * tort, or indemnity.
  19. *
  20. * This program is free software; you can redistribute it and/or modify
  21. * it under the terms of the GNU General Public License as published by
  22. * the Free Software Foundation; either version 2 of the License, or
  23. * (at your option) any later version.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  28. *
  29. * author(s) : Joe deBlaquiere
  30. */
  31. #ifndef __NETARM_MEM_MODULE_REGISTERS_H
  32. #define __NETARM_MEM_MODULE_REGISTERS_H
  33. /* GEN unit register offsets */
  34. #define NETARM_MEM_MODULE_BASE (0xFFC00000)
  35. #define NETARM_MEM_MODULE_CONFIG (0x00)
  36. #define NETARM_MEM_CS0_BASE_ADDR (0x10)
  37. #define NETARM_MEM_CS0_OPTIONS (0x14)
  38. #define NETARM_MEM_CS1_BASE_ADDR (0x20)
  39. #define NETARM_MEM_CS1_OPTIONS (0x24)
  40. #define NETARM_MEM_CS2_BASE_ADDR (0x30)
  41. #define NETARM_MEM_CS2_OPTIONS (0x34)
  42. #define NETARM_MEM_CS3_BASE_ADDR (0x40)
  43. #define NETARM_MEM_CS3_OPTIONS (0x44)
  44. #define NETARM_MEM_CS4_BASE_ADDR (0x50)
  45. #define NETARM_MEM_CS4_OPTIONS (0x54)
  46. /* select bitfield defintions */
  47. /* Module Configuration Register ( 0xFFC0_0000 ) */
  48. #define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000)
  49. #define NETARM_MEM_CFG_REFRESH_EN (0x00800000)
  50. #define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000)
  51. #define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000)
  52. #define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000)
  53. #define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000)
  54. #define NETARM_MEM_CFG_PORTC_AMUX (0x00100000)
  55. #define NETARM_MEM_CFG_A27_ADDR (0x00080000)
  56. #define NETARM_MEM_CFG_A27_CS0OE (0x00000000)
  57. #define NETARM_MEM_CFG_A26_ADDR (0x00040000)
  58. #define NETARM_MEM_CFG_A26_CS0WE (0x00000000)
  59. #define NETARM_MEM_CFG_A25_ADDR (0x00020000)
  60. #define NETARM_MEM_CFG_A25_BLAST (0x00000000)
  61. #define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000)
  62. /* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
  63. /* the expression will round down, so make sure to reverse it to verify */
  64. /* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */
  65. /* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
  66. #define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \
  67. (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
  68. ) - (1) ) << (24)))
  69. #if 0
  70. /* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
  71. /* the expression will round down, so make sure to reverse it toverify */
  72. /* it is what you want. period = [( count + 1 ) * 4] / Fxtal */
  73. #define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \
  74. (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
  75. ) - (1) ) << (24)))
  76. #endif
  77. /* Base Address Registers (0xFFC0_00X0) */
  78. #define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000)
  79. /* macro to define base */
  80. #define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK)
  81. #define NETARM_MEM_BAR_DRAM_FP (0x00000000)
  82. #define NETARM_MEM_BAR_DRAM_EDO (0x00000100)
  83. #define NETARM_MEM_BAR_DRAM_SYNC (0x00000200)
  84. #define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000)
  85. #define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080)
  86. #define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000)
  87. #define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020)
  88. #define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010)
  89. #define NETARM_MEM_BAR_DRAM_SEL (0x00000008)
  90. #define NETARM_MEM_BAR_BURST_EN (0x00000004)
  91. #define NETARM_MEM_BAR_WRT_PROT (0x00000002)
  92. #define NETARM_MEM_BAR_VALID (0x00000001)
  93. /* Option Registers (0xFFC0_00X4) */
  94. /* macro to define which bits of the base are significant */
  95. #define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK)
  96. #define NETARM_MEM_OPT_WAIT_MASK (0x00000F00)
  97. #define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
  98. #define NETARM_MEM_OPT_BCYC_1 (0x00000000)
  99. #define NETARM_MEM_OPT_BCYC_2 (0x00000040)
  100. #define NETARM_MEM_OPT_BCYC_3 (0x00000080)
  101. #define NETARM_MEM_OPT_BCYC_4 (0x000000C0)
  102. #define NETARM_MEM_OPT_BSIZE_2 (0x00000000)
  103. #define NETARM_MEM_OPT_BSIZE_4 (0x00000010)
  104. #define NETARM_MEM_OPT_BSIZE_8 (0x00000020)
  105. #define NETARM_MEM_OPT_BSIZE_16 (0x00000030)
  106. #define NETARM_MEM_OPT_32BIT (0x00000000)
  107. #define NETARM_MEM_OPT_16BIT (0x00000004)
  108. #define NETARM_MEM_OPT_8BIT (0x00000008)
  109. #define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C)
  110. #define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C)
  111. #define NETARM_MEM_OPT_READ_ASYNC (0x00000000)
  112. #define NETARM_MEM_OPT_READ_SYNC (0x00000002)
  113. #define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000)
  114. #define NETARM_MEM_OPT_WRITE_SYNC (0x00000001)
  115. #endif