csb272.c 4.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174
  1. /*
  2. * (C) Copyright 2004
  3. * Tolunay Orkun, Nextio Inc., torkun@nextio.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <asm/u-boot.h>
  24. #include <asm/processor.h>
  25. #include <common.h>
  26. #include <i2c.h>
  27. #include <miiphy.h>
  28. #include <405gp_enet.h>
  29. /*
  30. * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
  31. *
  32. * CLKA output => Epson LCD Controller
  33. * CLKB output => Not Connected
  34. * CLKC output => Ethernet
  35. * CLKD output => UART external clock
  36. *
  37. * Note: these values are obtained from device after init by micromonitor
  38. */
  39. uchar pll_fs6377_regs[16] = {
  40. 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
  41. 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
  42. /*
  43. * pll_init: Initialize AMIS IC FS6377-01 PLL
  44. *
  45. * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
  46. *
  47. */
  48. int pll_init(void)
  49. {
  50. i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
  51. return i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
  52. (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
  53. }
  54. /*
  55. * board_pre_init: do any preliminary board initialization
  56. *
  57. */
  58. int board_pre_init(void)
  59. {
  60. /* initialize PLL so UART, LCD, Ethernet clocked at correctly */
  61. (void) get_clocks();
  62. pll_init();
  63. /*-------------------------------------------------------------------------+
  64. | Interrupt controller setup for the Walnut board.
  65. | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  66. | IRQ 16 405GP internally generated; active low; level sensitive
  67. | IRQ 17-24 RESERVED
  68. | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  69. | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  70. | IRQ 27 (EXT IRQ 2) Not Used
  71. | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  72. | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  73. | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  74. | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  75. | Note for Walnut board:
  76. | An interrupt taken for the FPGA (IRQ 25) indicates that either
  77. | the Mouse, Keyboard, IRDA, or External Expansion caused the
  78. | interrupt. The FPGA must be read to determine which device
  79. | caused the interrupt. The default setting of the FPGA clears
  80. |
  81. +-------------------------------------------------------------------------*/
  82. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  83. mtdcr (uicer, 0x00000000); /* disable all ints */
  84. mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
  85. mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
  86. mtdcr (uictr, 0x10000000); /* set int trigger levels */
  87. mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
  88. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  89. mtebc (epcr, 0xa8400000); /* EBC always driven */
  90. return 0; /* success */
  91. }
  92. /*
  93. * checkboard: identify/verify the board we are running
  94. *
  95. * Remark: we just assume it is correct board here!
  96. *
  97. */
  98. int checkboard(void)
  99. {
  100. printf("BOARD: Cogent CSB272\n");
  101. return 0; /* success */
  102. }
  103. /*
  104. * initram: Determine the size of mounted DRAM
  105. *
  106. * Size is determined by reading SDRAM configuration registers as
  107. * configured by initialization code
  108. *
  109. */
  110. long initdram (int board_type)
  111. {
  112. ulong tot_size;
  113. ulong bank_size;
  114. ulong tmp;
  115. tot_size = 0;
  116. mtdcr (memcfga, mem_mb0cf);
  117. tmp = mfdcr (memcfgd);
  118. if (tmp & 0x00000001) {
  119. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  120. tot_size += bank_size;
  121. }
  122. mtdcr (memcfga, mem_mb1cf);
  123. tmp = mfdcr (memcfgd);
  124. if (tmp & 0x00000001) {
  125. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  126. tot_size += bank_size;
  127. }
  128. mtdcr (memcfga, mem_mb2cf);
  129. tmp = mfdcr (memcfgd);
  130. if (tmp & 0x00000001) {
  131. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  132. tot_size += bank_size;
  133. }
  134. mtdcr (memcfga, mem_mb3cf);
  135. tmp = mfdcr (memcfgd);
  136. if (tmp & 0x00000001) {
  137. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  138. tot_size += bank_size;
  139. }
  140. return tot_size;
  141. }
  142. /*
  143. * last_stage_init: final configurations (such as PHY etc)
  144. *
  145. */
  146. int last_stage_init(void)
  147. {
  148. /* initialize the PHY */
  149. miiphy_reset(CONFIG_PHY_ADDR);
  150. miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
  151. PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
  152. miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
  153. return 0; /* success */
  154. }