board.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * (C) Copyright 2016
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. *
  8. * Based on:
  9. * Board functions for TI AM335X based boards
  10. *
  11. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12. */
  13. #include <common.h>
  14. #include <bootstage.h>
  15. #include <cpu_func.h>
  16. #include <env.h>
  17. #include <errno.h>
  18. #include <init.h>
  19. #include <irq_func.h>
  20. #include <net.h>
  21. #include <spl.h>
  22. #include <asm/arch/cpu.h>
  23. #include <asm/arch/hardware.h>
  24. #include <asm/arch/omap.h>
  25. #include <asm/arch/ddr_defs.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/mmc_host_def.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/arch/mem.h>
  31. #include <asm/global_data.h>
  32. #include <asm/io.h>
  33. #include <asm/emif.h>
  34. #include <asm/gpio.h>
  35. #include <i2c.h>
  36. #include <miiphy.h>
  37. #include <cpsw.h>
  38. #include <linux/delay.h>
  39. #include <power/tps65217.h>
  40. #include <env_internal.h>
  41. #include <watchdog.h>
  42. #include "mmc.h"
  43. #include "board.h"
  44. DECLARE_GLOBAL_DATA_PTR;
  45. static struct shc_eeprom __section(".data") header;
  46. static int shc_eeprom_valid;
  47. /*
  48. * Read header information from EEPROM into global structure.
  49. */
  50. static int read_eeprom(void)
  51. {
  52. /* Check if baseboard eeprom is available */
  53. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  54. puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  55. return -ENODEV;
  56. }
  57. /* read the eeprom using i2c */
  58. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  59. sizeof(header))) {
  60. puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
  61. return -EIO;
  62. }
  63. if (header.magic != HDR_MAGIC) {
  64. printf("Incorrect magic number (0x%x) in EEPROM\n",
  65. header.magic);
  66. return -EIO;
  67. }
  68. shc_eeprom_valid = 1;
  69. return 0;
  70. }
  71. static void shc_request_gpio(void)
  72. {
  73. gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
  74. gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
  75. gpio_request(RESET_GPIO, "reset");
  76. gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
  77. gpio_request(WIFI_RST_GPIO, "WIFI rst");
  78. gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
  79. gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
  80. gpio_request(ENOC_RST_GPIO, "ENOC rst");
  81. #if defined CONFIG_B_SAMPLE
  82. gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
  83. gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
  84. gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
  85. gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
  86. #else
  87. gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
  88. gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
  89. gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
  90. gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
  91. gpio_request(LED_PWM_GPIO, "LED PWM");
  92. gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
  93. #endif
  94. gpio_request(BACK_BUTTON_GPIO, "Back button");
  95. gpio_request(FRONT_BUTTON_GPIO, "Front button");
  96. }
  97. /*
  98. * Function which forces all installed modules into running state for ICT
  99. * testing. Called by SPL.
  100. */
  101. static void __maybe_unused force_modules_running(void)
  102. {
  103. /* Wi-Fi power regulator enable - high = enabled */
  104. gpio_direction_output(WIFI_REGEN_GPIO, 1);
  105. /*
  106. * Wait for Wi-Fi power regulator to reach a stable voltage
  107. * (soft-start time, max. 350 µs)
  108. */
  109. __udelay(350);
  110. /* Wi-Fi module reset - high = running */
  111. gpio_direction_output(WIFI_RST_GPIO, 1);
  112. /* ZigBee reset - high = running */
  113. gpio_direction_output(ZIGBEE_RST_GPIO, 1);
  114. /* BidCos reset - high = running */
  115. gpio_direction_output(BIDCOS_RST_GPIO, 1);
  116. #if !defined(CONFIG_B_SAMPLE)
  117. /* Z-Wave reset - high = running */
  118. gpio_direction_output(Z_WAVE_RST_GPIO, 1);
  119. #endif
  120. /* EnOcean reset - low = running */
  121. gpio_direction_output(ENOC_RST_GPIO, 0);
  122. }
  123. /*
  124. * Function which forces all installed modules into reset - to be released by
  125. * the OS, called by SPL
  126. */
  127. static void __maybe_unused force_modules_reset(void)
  128. {
  129. /* Wi-Fi module reset - low = reset */
  130. gpio_direction_output(WIFI_RST_GPIO, 0);
  131. /* Wi-Fi power regulator enable - low = disabled */
  132. gpio_direction_output(WIFI_REGEN_GPIO, 0);
  133. /* ZigBee reset - low = reset */
  134. gpio_direction_output(ZIGBEE_RST_GPIO, 0);
  135. /* BidCos reset - low = reset */
  136. /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
  137. #if !defined(CONFIG_B_SAMPLE)
  138. /* Z-Wave reset - low = reset */
  139. gpio_direction_output(Z_WAVE_RST_GPIO, 0);
  140. #endif
  141. /* EnOcean reset - high = reset*/
  142. gpio_direction_output(ENOC_RST_GPIO, 1);
  143. }
  144. /*
  145. * Function to set the LEDs in the state "Bootloader booting"
  146. */
  147. static void __maybe_unused leds_set_booting(void)
  148. {
  149. #if defined(CONFIG_B_SAMPLE)
  150. /* Turn all red LEDs on */
  151. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  152. gpio_direction_output(LED_CONN_RD_GPIO, 1);
  153. #else /* All other SHCs starting with B2-Sample */
  154. /* Set the PWM GPIO */
  155. gpio_direction_output(LED_PWM_GPIO, 1);
  156. /* Turn all red LEDs on */
  157. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  158. gpio_direction_output(LED_LAN_RD_GPIO, 1);
  159. gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
  160. #endif
  161. }
  162. /*
  163. * Function to set the LEDs in the state "Bootloader error"
  164. */
  165. static void __maybe_unused leds_set_failure(int state)
  166. {
  167. #if defined(CONFIG_B_SAMPLE)
  168. /* Turn all blue and green LEDs off */
  169. gpio_set_value(LED_PWR_BL_GPIO, 0);
  170. gpio_set_value(LED_PWR_GN_GPIO, 0);
  171. gpio_set_value(LED_CONN_BL_GPIO, 0);
  172. gpio_set_value(LED_CONN_GN_GPIO, 0);
  173. /* Turn all red LEDs to 'state' */
  174. gpio_set_value(LED_PWR_RD_GPIO, state);
  175. gpio_set_value(LED_CONN_RD_GPIO, state);
  176. #else /* All other SHCs starting with B2-Sample */
  177. /* Set the PWM GPIO */
  178. gpio_direction_output(LED_PWM_GPIO, 1);
  179. /* Turn all blue LEDs off */
  180. gpio_set_value(LED_PWR_BL_GPIO, 0);
  181. gpio_set_value(LED_LAN_BL_GPIO, 0);
  182. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  183. /* Turn all red LEDs to 'state' */
  184. gpio_set_value(LED_PWR_RD_GPIO, state);
  185. gpio_set_value(LED_LAN_RD_GPIO, state);
  186. gpio_set_value(LED_CLOUD_RD_GPIO, state);
  187. #endif
  188. }
  189. /*
  190. * Function to set the LEDs in the state "Bootloader finished"
  191. */
  192. static void leds_set_finish(void)
  193. {
  194. #if defined(CONFIG_B_SAMPLE)
  195. /* Turn all LEDs off */
  196. gpio_set_value(LED_PWR_BL_GPIO, 0);
  197. gpio_set_value(LED_PWR_RD_GPIO, 0);
  198. gpio_set_value(LED_PWR_GN_GPIO, 0);
  199. gpio_set_value(LED_CONN_BL_GPIO, 0);
  200. gpio_set_value(LED_CONN_RD_GPIO, 0);
  201. gpio_set_value(LED_CONN_GN_GPIO, 0);
  202. #else /* All other SHCs starting with B2-Sample */
  203. /* Turn all LEDs off */
  204. gpio_set_value(LED_PWR_BL_GPIO, 0);
  205. gpio_set_value(LED_PWR_RD_GPIO, 0);
  206. gpio_set_value(LED_LAN_BL_GPIO, 0);
  207. gpio_set_value(LED_LAN_RD_GPIO, 0);
  208. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  209. gpio_set_value(LED_CLOUD_RD_GPIO, 0);
  210. /* Turn off the PWM GPIO and mux it to EHRPWM */
  211. gpio_set_value(LED_PWM_GPIO, 0);
  212. enable_shc_board_pwm_pin_mux();
  213. #endif
  214. }
  215. static void check_button_status(void)
  216. {
  217. ulong value;
  218. gpio_direction_input(FRONT_BUTTON_GPIO);
  219. value = gpio_get_value(FRONT_BUTTON_GPIO);
  220. if (value == 0) {
  221. printf("front button activated !\n");
  222. env_set("harakiri", "1");
  223. }
  224. }
  225. #if defined(CONFIG_SPL_BUILD)
  226. #ifdef CONFIG_SPL_OS_BOOT
  227. int spl_start_uboot(void)
  228. {
  229. return 1;
  230. }
  231. #endif
  232. static void shc_board_early_init(void)
  233. {
  234. shc_request_gpio();
  235. # ifdef CONFIG_SHC_ICT
  236. /* Force all modules into enabled state for ICT testing */
  237. force_modules_running();
  238. # else
  239. /* Force all modules to enter Reset state until released by the OS */
  240. force_modules_reset();
  241. # endif
  242. leds_set_booting();
  243. }
  244. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  245. #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
  246. #define OSC (V_OSCK/1000000)
  247. /* Bosch: Predivider must be fixed to 4, so N = 4-1 */
  248. #define MPUPLL_N (4-1)
  249. /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
  250. #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
  251. const struct dpll_params dpll_ddr_shc = {
  252. 400, OSC-1, 1, -1, -1, -1, -1};
  253. const struct dpll_params *get_dpll_ddr_params(void)
  254. {
  255. return &dpll_ddr_shc;
  256. }
  257. /*
  258. * As we enabled downspread SSC with 1.8%, the values needed to be corrected
  259. * such that the 20% overshoot will not lead to too high frequencies.
  260. * In all cases, this is achieved by subtracting one from M (6 MHz less).
  261. * Example: 600 MHz CPU
  262. * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
  263. * 600 MHz - 6 MHz (1x Fref) = 594 MHz
  264. * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
  265. * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
  266. * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
  267. */
  268. const struct dpll_params dpll_mpu_shc_opp100 = {
  269. 99, MPUPLL_N, 1, -1, -1, -1, -1};
  270. void am33xx_spl_board_init(void)
  271. {
  272. int sil_rev;
  273. int mpu_vdd;
  274. puts(BOARD_ID_STR);
  275. /*
  276. * Set CORE Frequency to OPP100
  277. * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
  278. */
  279. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  280. sil_rev = readl(&cdev->deviceid) >> 28;
  281. if (sil_rev < 2) {
  282. puts("We do not support Silicon Revisions below 2.0!\n");
  283. return;
  284. }
  285. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  286. if (i2c_probe(TPS65217_CHIP_PM))
  287. return;
  288. /*
  289. * Retrieve the CPU max frequency by reading the efuse
  290. * SHC-Default: 600 MHz
  291. */
  292. switch (dpll_mpu_opp100.m) {
  293. case MPUPLL_M_1000:
  294. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  295. break;
  296. case MPUPLL_M_800:
  297. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  298. break;
  299. case MPUPLL_M_720:
  300. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  301. break;
  302. case MPUPLL_M_600:
  303. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  304. break;
  305. case MPUPLL_M_300:
  306. mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
  307. break;
  308. default:
  309. puts("Cannot determine the frequency, failing!\n");
  310. return;
  311. }
  312. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  313. puts("tps65217_voltage_update failure\n");
  314. return;
  315. }
  316. /* Set MPU Frequency to what we detected */
  317. printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
  318. printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
  319. dpll_mpu_shc_opp100.m);
  320. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
  321. /* Enable Spread Spectrum for this freq to be clean on EMI side */
  322. set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
  323. /*
  324. * Using the default voltages for the PMIC (TPS65217D)
  325. * LS1 = 1.8V (VDD_1V8)
  326. * LS2 = 3.3V (VDD_3V3A)
  327. * LDO1 = 1.8V (VIO and VRTC)
  328. * LDO2 = 3.3V (VDD_3V3AUX)
  329. */
  330. shc_board_early_init();
  331. }
  332. void set_uart_mux_conf(void)
  333. {
  334. enable_uart0_pin_mux();
  335. }
  336. void set_mux_conf_regs(void)
  337. {
  338. enable_shc_board_pin_mux();
  339. }
  340. const struct ctrl_ioregs ioregs_evmsk = {
  341. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  342. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  343. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  344. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  345. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  346. };
  347. static const struct ddr_data ddr3_shc_data = {
  348. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  349. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  350. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  351. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  352. };
  353. static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
  354. .cmd0csratio = MT41K256M16HA125E_RATIO,
  355. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  356. .cmd1csratio = MT41K256M16HA125E_RATIO,
  357. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  358. .cmd2csratio = MT41K256M16HA125E_RATIO,
  359. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  360. };
  361. static struct emif_regs ddr3_shc_emif_reg_data = {
  362. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  363. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  364. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  365. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  366. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  367. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  368. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
  369. PHY_EN_DYN_PWRDN,
  370. };
  371. void sdram_init(void)
  372. {
  373. /* Configure the DDR3 RAM */
  374. config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
  375. &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
  376. }
  377. #endif
  378. /*
  379. * Basic board specific setup. Pinmux has been handled already.
  380. */
  381. int board_init(void)
  382. {
  383. #if defined(CONFIG_HW_WATCHDOG)
  384. hw_watchdog_init();
  385. #endif
  386. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  387. if (read_eeprom() < 0)
  388. puts("EEPROM Content Invalid.\n");
  389. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  390. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  391. gpmc_init();
  392. #endif
  393. shc_request_gpio();
  394. return 0;
  395. }
  396. #ifdef CONFIG_BOARD_LATE_INIT
  397. int board_late_init(void)
  398. {
  399. check_button_status();
  400. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  401. if (shc_eeprom_valid)
  402. if (is_valid_ethaddr(header.mac_addr))
  403. eth_env_set_enetaddr("ethaddr", header.mac_addr);
  404. #endif
  405. return 0;
  406. }
  407. #endif
  408. #if defined(CONFIG_USB_ETHER) && \
  409. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
  410. int board_eth_init(struct bd_info *bis)
  411. {
  412. return usb_eth_initialize(bis);
  413. }
  414. #endif
  415. #if CONFIG_IS_ENABLED(BOOTSTAGE)
  416. static void bosch_check_reset_pin(void)
  417. {
  418. if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
  419. printf("Resetting ...\n");
  420. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  421. disable_interrupts();
  422. reset_cpu();
  423. /*NOTREACHED*/
  424. }
  425. }
  426. static void hang_bosch(const char *cause, int code)
  427. {
  428. int lv;
  429. gpio_direction_input(RESET_GPIO);
  430. /* Enable reset pin interrupt on falling edge */
  431. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  432. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
  433. enable_interrupts();
  434. puts(cause);
  435. for (;;) {
  436. for (lv = 0; lv < code; lv++) {
  437. bosch_check_reset_pin();
  438. leds_set_failure(1);
  439. __udelay(150 * 1000);
  440. leds_set_failure(0);
  441. __udelay(150 * 1000);
  442. }
  443. #if defined(BLINK_CODE)
  444. __udelay(300 * 1000);
  445. #endif
  446. }
  447. }
  448. void show_boot_progress(int val)
  449. {
  450. switch (val) {
  451. case BOOTSTAGE_ID_NEED_RESET:
  452. hang_bosch("need reset", 4);
  453. break;
  454. }
  455. }
  456. #endif
  457. void arch_preboot_os(void)
  458. {
  459. leds_set_finish();
  460. }