cpu.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008-2011
  4. * Graeme Russ, <graeme.russ@gmail.com>
  5. *
  6. * (C) Copyright 2002
  7. * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  8. *
  9. * (C) Copyright 2002
  10. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  11. * Marius Groeger <mgroeger@sysgo.de>
  12. *
  13. * (C) Copyright 2002
  14. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  15. * Alex Zuepke <azu@sysgo.de>
  16. *
  17. * Part of this file is adapted from coreboot
  18. * src/arch/x86/lib/cpu.c
  19. */
  20. #define LOG_CATEGORY UCLASS_CPU
  21. #include <common.h>
  22. #include <bootstage.h>
  23. #include <command.h>
  24. #include <cpu_func.h>
  25. #include <dm.h>
  26. #include <errno.h>
  27. #include <init.h>
  28. #include <irq.h>
  29. #include <log.h>
  30. #include <malloc.h>
  31. #include <syscon.h>
  32. #include <acpi/acpi_s3.h>
  33. #include <acpi/acpi_table.h>
  34. #include <asm/acpi.h>
  35. #include <asm/control_regs.h>
  36. #include <asm/coreboot_tables.h>
  37. #include <asm/cpu.h>
  38. #include <asm/global_data.h>
  39. #include <asm/lapic.h>
  40. #include <asm/microcode.h>
  41. #include <asm/mp.h>
  42. #include <asm/mrccache.h>
  43. #include <asm/msr.h>
  44. #include <asm/mtrr.h>
  45. #include <asm/post.h>
  46. #include <asm/processor.h>
  47. #include <asm/processor-flags.h>
  48. #include <asm/interrupt.h>
  49. #include <asm/tables.h>
  50. #include <linux/compiler.h>
  51. DECLARE_GLOBAL_DATA_PTR;
  52. #ifndef CONFIG_TPL_BUILD
  53. static const char *const x86_vendor_name[] = {
  54. [X86_VENDOR_INTEL] = "Intel",
  55. [X86_VENDOR_CYRIX] = "Cyrix",
  56. [X86_VENDOR_AMD] = "AMD",
  57. [X86_VENDOR_UMC] = "UMC",
  58. [X86_VENDOR_NEXGEN] = "NexGen",
  59. [X86_VENDOR_CENTAUR] = "Centaur",
  60. [X86_VENDOR_RISE] = "Rise",
  61. [X86_VENDOR_TRANSMETA] = "Transmeta",
  62. [X86_VENDOR_NSC] = "NSC",
  63. [X86_VENDOR_SIS] = "SiS",
  64. };
  65. #endif
  66. int __weak x86_cleanup_before_linux(void)
  67. {
  68. int ret;
  69. ret = mp_park_aps();
  70. if (ret)
  71. return log_msg_ret("park", ret);
  72. bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
  73. CONFIG_BOOTSTAGE_STASH_SIZE);
  74. return 0;
  75. }
  76. int x86_init_cache(void)
  77. {
  78. enable_caches();
  79. return 0;
  80. }
  81. int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
  82. void flush_cache(unsigned long dummy1, unsigned long dummy2)
  83. {
  84. asm("wbinvd\n");
  85. }
  86. /* Define these functions to allow ehch-hcd to function */
  87. void flush_dcache_range(unsigned long start, unsigned long stop)
  88. {
  89. }
  90. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  91. {
  92. }
  93. void dcache_enable(void)
  94. {
  95. enable_caches();
  96. }
  97. void dcache_disable(void)
  98. {
  99. disable_caches();
  100. }
  101. void icache_enable(void)
  102. {
  103. }
  104. void icache_disable(void)
  105. {
  106. }
  107. int icache_status(void)
  108. {
  109. return 1;
  110. }
  111. #ifndef CONFIG_TPL_BUILD
  112. const char *cpu_vendor_name(int vendor)
  113. {
  114. const char *name;
  115. name = "<invalid cpu vendor>";
  116. if (vendor < ARRAY_SIZE(x86_vendor_name) &&
  117. x86_vendor_name[vendor])
  118. name = x86_vendor_name[vendor];
  119. return name;
  120. }
  121. #endif
  122. char *cpu_get_name(char *name)
  123. {
  124. unsigned int *name_as_ints = (unsigned int *)name;
  125. struct cpuid_result regs;
  126. char *ptr;
  127. int i;
  128. /* This bit adds up to 48 bytes */
  129. for (i = 0; i < 3; i++) {
  130. regs = cpuid(0x80000002 + i);
  131. name_as_ints[i * 4 + 0] = regs.eax;
  132. name_as_ints[i * 4 + 1] = regs.ebx;
  133. name_as_ints[i * 4 + 2] = regs.ecx;
  134. name_as_ints[i * 4 + 3] = regs.edx;
  135. }
  136. name[CPU_MAX_NAME_LEN - 1] = '\0';
  137. /* Skip leading spaces. */
  138. ptr = name;
  139. while (*ptr == ' ')
  140. ptr++;
  141. return ptr;
  142. }
  143. int default_print_cpuinfo(void)
  144. {
  145. printf("CPU: %s, vendor %s, device %xh\n",
  146. cpu_has_64bit() ? "x86_64" : "x86",
  147. cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
  148. if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
  149. debug("ACPI previous sleep state: %s\n",
  150. acpi_ss_string(gd->arch.prev_sleep_state));
  151. }
  152. return 0;
  153. }
  154. #if CONFIG_IS_ENABLED(BOOTSTAGE)
  155. void show_boot_progress(int val)
  156. {
  157. outb(val, POST_PORT);
  158. }
  159. #endif
  160. #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
  161. /*
  162. * Implement a weak default function for boards that need to do some final init
  163. * before the system is ready.
  164. */
  165. __weak void board_final_init(void)
  166. {
  167. }
  168. /*
  169. * Implement a weak default function for boards that need to do some final
  170. * processing before booting the OS.
  171. */
  172. __weak void board_final_cleanup(void)
  173. {
  174. }
  175. int last_stage_init(void)
  176. {
  177. struct acpi_fadt __maybe_unused *fadt;
  178. int ret;
  179. board_final_init();
  180. if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
  181. fadt = acpi_find_fadt();
  182. if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
  183. acpi_resume(fadt);
  184. }
  185. ret = write_tables();
  186. if (ret) {
  187. log_err("Failed to write tables\n");
  188. return log_msg_ret("table", ret);
  189. }
  190. if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
  191. fadt = acpi_find_fadt();
  192. /* Don't touch ACPI hardware on HW reduced platforms */
  193. if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
  194. /*
  195. * Other than waiting for OSPM to request us to switch
  196. * to ACPI * mode, do it by ourselves, since SMI will
  197. * not be triggered.
  198. */
  199. enter_acpi_mode(fadt->pm1a_cnt_blk);
  200. }
  201. }
  202. /*
  203. * TODO(sjg@chromium.org): Move this to bootm_announce_and_cleanup()
  204. * once APL FSP-S at 0x200000 does not overlap with the bzimage at
  205. * 0x100000.
  206. */
  207. board_final_cleanup();
  208. return 0;
  209. }
  210. #endif
  211. static int x86_init_cpus(void)
  212. {
  213. if (IS_ENABLED(CONFIG_SMP)) {
  214. debug("Init additional CPUs\n");
  215. x86_mp_init();
  216. } else {
  217. struct udevice *dev;
  218. /*
  219. * This causes the cpu-x86 driver to be probed.
  220. * We don't check return value here as we want to allow boards
  221. * which have not been converted to use cpu uclass driver to
  222. * boot.
  223. */
  224. uclass_first_device(UCLASS_CPU, &dev);
  225. }
  226. return 0;
  227. }
  228. int cpu_init_r(void)
  229. {
  230. struct udevice *dev;
  231. int ret;
  232. if (!ll_boot_init()) {
  233. uclass_first_device(UCLASS_PCI, &dev);
  234. return 0;
  235. }
  236. ret = x86_init_cpus();
  237. if (ret)
  238. return ret;
  239. /*
  240. * Set up the northbridge, PCH and LPC if available. Note that these
  241. * may have had some limited pre-relocation init if they were probed
  242. * before relocation, but this is post relocation.
  243. */
  244. uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
  245. uclass_first_device(UCLASS_PCH, &dev);
  246. uclass_first_device(UCLASS_LPC, &dev);
  247. /* Set up pin control if available */
  248. ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
  249. debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
  250. return 0;
  251. }
  252. #ifndef CONFIG_EFI_STUB
  253. int reserve_arch(void)
  254. {
  255. struct udevice *itss;
  256. int ret;
  257. if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
  258. mrccache_reserve();
  259. if (IS_ENABLED(CONFIG_SEABIOS))
  260. high_table_reserve();
  261. if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
  262. acpi_s3_reserve();
  263. if (IS_ENABLED(CONFIG_HAVE_FSP)) {
  264. /*
  265. * Save stack address to CMOS so that at next S3 boot,
  266. * we can use it as the stack address for fsp_contiue()
  267. */
  268. fsp_save_s3_stack();
  269. }
  270. }
  271. ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  272. if (!ret) {
  273. /*
  274. * Snapshot the current GPIO IRQ polarities. FSP-S is about to
  275. * run and will set a default policy that doesn't honour boards'
  276. * requirements
  277. */
  278. irq_snapshot_polarities(itss);
  279. }
  280. return 0;
  281. }
  282. #endif
  283. long detect_coreboot_table_at(ulong start, ulong size)
  284. {
  285. u32 *ptr, *end;
  286. size /= 4;
  287. for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
  288. if (*ptr == 0x4f49424c) /* "LBIO" */
  289. return (long)ptr;
  290. }
  291. return -ENOENT;
  292. }
  293. long locate_coreboot_table(void)
  294. {
  295. long addr;
  296. /* We look for LBIO in the first 4K of RAM and again at 960KB */
  297. addr = detect_coreboot_table_at(0x0, 0x1000);
  298. if (addr < 0)
  299. addr = detect_coreboot_table_at(0xf0000, 0x1000);
  300. return addr;
  301. }